Zeljko Zilic
Zeljko Zilic
Professor of Electrical and Computer Engineering
Verified email at mcgill.ca - Homepage
Title
Cited by
Cited by
Year
Assertion checkers in verification, silicon debug and in-field diagnosis
M Boule, JS Chenard, Z Zilic
8th International Symposium on Quality Electronic Design (ISQED'07), 613-620, 2007
1982007
Adding debug enhancements to assertion checkers for hardware emulation and silicon debug
M Boulé, JS Chenard, Z Zilic
2006 International Conference on Computer Design, 294-299, 2006
1692006
Using BDDs to Design ULMs for FPGAs
Z Zilic, ZG Vranesic
Proceedings of the 1996 ACM fourth international symposium on Field …, 1996
1271996
A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing
S Bourduas, Z Zilic
First International Symposium on Networks-on-Chip (NOCS'07), 195-204, 2007
1232007
Generating hardware assertion checkers
M Boulé, Z Zilic
Springer, 2008
1092008
Automata-based assertion-checker synthesis of PSL properties
M Boulé, Z Zilic
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008
1022008
A comprehensive analysis on wearable acceleration sensors in human activity recognition
M Janidarmian, A Roshan Fekr, K Radecka, Z Zilic
Sensors 17 (3), 529, 2017
952017
Incorporating efficient assertion checkers into hardware emulation
M Boule, Z Zilic
2005 International Conference on Computer Design, 221-228, 2005
812005
The NUMAchine multiprocessor
ZG Vranesic, S Brown, M Stumm, S Caranci, A Grbic, R Grindley, M Gusat, ...
University of Toronto. Computer Systems Research Institute, 1995
781995
Echo cancellation in IP networks
J Radecki, Z Zilic, K Radecka
The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002 …, 2002
762002
Architectures of increased availability wireless sensor network nodes
MW Chiang, Z Zilic, K Radecka, JS Chenard
2004 International Conferce on Test, 1232-1241, 2004
752004
Efficient automata-based assertion-checker synthesis of PSL properties
M Boulé, Z Zilic
2006 IEEE International High Level Design Validation and Test Workshop, 69-76, 2006
742006
FPGA emulation of quantum circuits
AU Khalid, Z Zilic, K Radecka
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
682004
Automata unit, a tool for designing checker circuitry and a method of manufacturing hardware circuitry incorporating checker circuitry
Z Zilic, M Boulé
US Patent 8,024,691, 2011
632011
Reliability aware NoC router architecture using input channel buffer sharing
MH Neishaburi, Z Zilic
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 511-516, 2009
572009
A laboratory setup and teaching methodology for wireless and mobile embedded systems
JS Chenard, Z Zilic, M Prokic
IEEE Transactions on Education 51 (3), 378-384, 2008
572008
Migration and economy: global and local dynamics
L Trager
Rowman Altamira, 2005
572005
Dynamic clock management for low power applications in FPGAs
I Brynjolfson, Z Zilic
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No …, 2000
482000
The NUMAchine multiprocessor
R Grindley, T Abdelrahman, S Brown, S Caranci, D DeVries, B Gamsa, ...
Proceedings 2000 International Conference on Parallel Processing, 487-496, 2000
462000
Multiple-valued logic in FPGAs
Z Zilic, ZG Vranesic
Proceedings of 36th Midwest Symposium on Circuits and Systems, 1553-1556, 1993
451993
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Articles 1–20