Etienne Nowak
Etienne Nowak
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A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration
A Hubert, E Nowak, K Tachi, V Maffini-Alvaro, C Vizioz, C Arvet, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Intrinsic fluctuations in vertical NAND flash memories
E Nowak, JH Kim, HY Kwon, YG Kim, JS Sim, SH Lim, DS Kim, KH Lee, ...
2012 Symposium on VLSI Technology (VLSIT), 21-22, 2012
Fundamental variability limits of filament-based RRAM
A Grossi, E Nowak, C Zambelli, C Pellissier, S Bernasconi, G Cibrario, ...
2016 IEEE International Electron Devices Meeting (IEDM), 4.7. 1-4.7. 4, 2016
In-memory and error-immune differential rram implementation of binarized deep neural networks
M Bocquet, T Hirztlin, JO Klein, E Nowak, E Vianello, JM Portal, ...
2018 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2018
Experimental investigation of 4-kb RRAM arrays programming conditions suitable for TCAM
A Grossi, E Vianello, C Zambelli, P Royer, JP Noel, B Giraud, L Perniola, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
Experimental demonstration of short and long term synaptic plasticity using OxRAM multi k-bit arrays for reliable detection in highly noisy input data
T Werner, E Vianello, O Bichler, A Grossi, E Nowak, JF Nodin, B Yvert, ...
2016 IEEE International Electron Devices Meeting (IEDM), 16.6. 1-16.6. 4, 2016
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications
G Sassine, C Nail, L Tillie, DA Robayo, A Levisse, C Cagli, KE Hajjam, ...
2018 IEEE International Reliability Physics Symposium (IRPS), P-MY. 2-1-P-MY …, 2018
Narrow Heater Bottom Electrode‐Based Phase Change Memory as a Bidirectional Artificial Synapse
S La Barbera, DRB Ly, G Navarro, N Castellani, O Cueto, G Bourgeois, ...
Advanced Electronic Materials 4 (9), 1800223, 2018
Advantages of the FinFET architecture in SONOS and nanocrystal memory devices
S Lombardo, C Gerardi, L Breuil, C Jahan, L Perniola, G Cina, D Corso, ...
2007 IEEE International Electron Devices Meeting, 921-924, 2007
Resistive RAM endurance: Array-level characterization and correction techniques targeting deep learning applications
A Grossi, E Vianello, MM Sabry, M Barlas, L Grenouillet, J Coignus, ...
IEEE Transactions on Electron Devices 66 (3), 1281-1288, 2019
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
L Masoero, G Molas, F Brun, M Gély, JP Colonna, V Della Marca, O Cueto, ...
2011 International Electron Devices Meeting, 9.5. 1-9.5. 4, 2011
Digital biologically plausible implementation of binarized neural networks with differential hafnium oxide resistive memory arrays
T Hirtzlin, M Bocquet, B Penkovsky, JO Klein, E Nowak, E Vianello, ...
Frontiers in neuroscience 13, 1383, 2020
Role of synaptic variability in resistive memory-based spiking neural networks with unsupervised learning
DRB Ly, A Grossi, C Fenouillet-Beranger, E Nowak, D Querlioz, ...
Journal of Physics D: Applied Physics 51 (44), 444002, 2018
In-depth analysis of 3D silicon nanowire SONOS memory characteristics by TCAD simulations
E Nowak, A Hubert, L Perniola, T Ernst, G Ghibaudo, G Reimbold, ...
2010 IEEE International Memory Workshop, 1-4, 2010
Performance and reliability of a 4Mb Si nanocrystal NOR Flash memory with optimized 1T memory cells
C Gerardi, G Molas, G Albini, E Tripiciano, M Gely, A Emmi, O Fiore, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold Switching (OTS) selectors
M Alayan, E Vianello, G Navarro, C Carabasse, S La Barbera, A Verdy, ...
2017 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2017
Universal Signatures from Non-Universal Memories: Clues for the Future...
L Perniola, G Molas, G Navarro, E Nowak, V Sousa, E Vianello, ...
2016 IEEE 8th International Memory Workshop (IMW), 1-3, 2016
Hybrid‐RRAM toward next generation of nonvolatile memory: coupling of oxygen vacancies and metal ions
G Sassine, C Nail, P Blaise, B Sklenard, M Bernard, R Gassilloud, A Marty, ...
Advanced Electronic Materials 5 (2), 1800658, 2019
Investigation of the role of H-related defects in Al2O3blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling
G Molas, L Masoero, P Blaise, A Padovani, JP Colonna, E Vianello, ...
2010 International Electron Devices Meeting, 22.5. 1-22.5. 4, 2010
Optimized reading window for crossbar arrays thanks to Ge-Se-Sb-N-based OTS selectors
A Verdy, M Bernard, J Garrione, G Bourgeois, MC Cyrille, E Nolot, ...
2018 IEEE International Electron Devices Meeting (IEDM), 37.4. 1-37.4. 4, 2018
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