Pablo Prieto
Title
Cited by
Cited by
Year
Rotary router: an efficient architecture for CMP interconnection networks
P Abad, V Puente, JA Gregorio, P Prieto
Proceedings of the 34th annual international symposium on Computer …, 2007
1112007
Topaz: An open-source interconnection network simulator for chip multiprocessors and supercomputers
P Abad, P Prieto, LG Menezo, V Puente, JÁ Gregorio
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 99-106, 2012
932012
SP-NUCA: a cost effective dynamic non-uniform cache architecture
J Merino, V Puente, P Prieto, JÁ Gregorio
ACM SIGARCH Computer Architecture News 36 (2), 64-71, 2008
422008
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory
P Abad, P Prieto, V Puente, JA Gregorio
IEEE Transactions on Parallel and Distributed Systems 27 (1), 66-77, 2015
102015
PARADIME: PARALLEL DISTRIBUTED INFRASTRUCTURE FOR MINIMIZATION OF ENERGY FOR DATA CENTERS
SK RETHINAGIRI, O Palomar, A Sobe, G Yalcin, T Knauth, R Titos Gil, ...
MICROPROCESSORS AND MICROSYSTEMS 39, 16, 2015
102015
CMP off-chip bandwidth scheduling guided by instruction criticality
P Prieto, V Puente, JA Gregorio
Proceedings of the 27th international ACM conference on International …, 2013
102013
Multilevel cache modeling for chip-multiprocessor systems
P Prieto, V Puente, JA Gregorio
IEEE Computer Architecture Letters 10 (2), 49-52, 2011
102011
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation
A Colaso, P Prieto, JA Herrero, P Abad, LG Menezo, V Puente, ...
IEEE Transactions on Parallel and Distributed Systems 29 (5), 1161-1173, 2017
52017
Improving last level shared cache performance through mobile insertion policies (MIP)
P Abad, P Prieto, V Puente, JA Gregorio
Parallel Computing 49, 13-27, 2015
42015
ENERGY MINIMIZATION AT ALL LAYERS OF THE DATA CENTER: THE PARADIME PROJECT
O Palomar, SK Rethinagiri, G Yalcin, R Titos-Gil, P Prieto, E Torrella, ...
19TH CONFERENCE ON DESIGN, AUTOMATION AND TEST IN EUROPE (DATE 2016), 2016
32016
Interaction of NoC design and Coherence Protocol in 3D-stacked CMPs
P Abad, P Prieto, LG Menezo, A Colaso, V Puente, JA Gregorio
2013 Euromicro Conference on Digital System Design, 48-55, 2013
22013
Topology-aware CMP design
P Prieto, V Puente, J Gregorio
Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC), 2009
22009
The gem5 Simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
12020
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip
P Abad, P Prieto, V Puente, JA Gregorio
2012 IEEE 30th International Conference on Computer Design (ICCD), 55-60, 2012
12012
Implementación de un protocolo de coherencia basado en token en el simulador GEMS
J Merino, LG Menezo, P Prieto, V Puente
XIX Jornadas del Paralelismo, 2008
12008
Towards a Shared/Private Non-Uniform Cache Architecture in CMP Systems
J Merino, V Puente, P Prieto, JÁ Gregorio
Fourth International Summer School on Advanced Computer Architecture and …, 2008
12008
SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads
P Prieto, P Abad, JA Herrero, JA Gregorio, V Puente
49th International Conference on Parallel Processing-ICPP, 1-11, 2020
2020
Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms
A Colaso, P Prieto, P Abad, JA Gregorio, V Puente
2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019
2019
Memory hierarchy characterization of NoSQL applications through full-system simulation
A Colaso Diego, P Prieto Torralbo, JÁ Herrero Velasco, P Abad Fidalgo, ...
IEEE Computer Society, 2018
2018
Jerarquía de memoria escalable para sistemas multiprocesador en chip
P Prieto Torralbo
2014
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Articles 1–20