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Pablo Prieto
Pablo Prieto
Dirección de correo verificada de unican.es
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The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
2462020
Rotary router: an efficient architecture for CMP interconnection networks
P Abad, V Puente, JA Gregorio, P Prieto
Proceedings of the 34th annual international symposium on Computer …, 2007
1212007
Topaz: An open-source interconnection network simulator for chip multiprocessors and supercomputers
P Abad, P Prieto, LG Menezo, V Puente, JÁ Gregorio
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 99-106, 2012
1132012
Sp-nuca: a cost effective dynamic non-uniform cache architecture
J Merino, V Puente, P Prieto, JÁ Gregorio
ACM SIGARCH Computer Architecture News 36 (2), 64-71, 2008
522008
The gem5 simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
112020
CMP off-chip bandwidth scheduling guided by instruction criticality
P Prieto, V Puente, JA Gregorio
Proceedings of the 27th international ACM conference on International …, 2013
112013
PARADIME: PARALLEL DISTRIBUTED INFRASTRUCTURE FOR MINIMIZATION OF ENERGY FOR DATA CENTERS
SK RETHINAGIRI, O Palomar, A Sobe, G Yalcin, T Knauth, R Titos Gil, ...
MICROPROCESSORS AND MICROSYSTEMS 39, 16, 2015
102015
Architecting racetrack memory preshift through pattern-based prediction mechanisms
A Colaso, P Prieto, P Abad, JA Gregorio, V Puente
2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019
92019
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory
P Abad, P Prieto, V Puente, JA Gregorio
IEEE Transactions on Parallel and Distributed Systems 27 (1), 66-77, 2015
92015
Multilevel cache modeling for chip-multiprocessor systems
P Prieto, V Puente, JA Gregorio
IEEE Computer Architecture Letters 10 (2), 49-52, 2011
92011
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation
A Colaso, P Prieto, JA Herrero, P Abad, LG Menezo, V Puente, ...
IEEE Transactions on Parallel and Distributed Systems 29 (5), 1161-1173, 2017
72017
Improving last level shared cache performance through mobile insertion policies (MIP)
P Abad, P Prieto, V Puente, JA Gregorio
Parallel Computing 49, 13-27, 2015
62015
Top-down performance profiling on nvidia's gpus
A Saiz, P Prieto, P Abad, JA Gregorio, V Puente
2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2022
42022
Fast, accurate processor evaluation through heterogeneous, sample-based benchmarking
P Prieto, P Abad, JA Gregorio, V Puente
IEEE Transactions on Parallel and Distributed Systems 32 (12), 2983-2995, 2021
32021
SPECcast: A methodology for fast performance evaluation with SPEC CPU 2017 multiprogrammed workloads
P Prieto, P Abad, JA Herrero, JA Gregorio, V Puente
Proceedings of the 49th International Conference on Parallel Processing, 1-11, 2020
32020
ENERGY MINIMIZATION AT ALL LAYERS OF THE DATA CENTER: THE PARADIME PROJECT
O Palomar, SK Rethinagiri, G Yalcin, R Titos-Gil, P Prieto, E Torrella, ...
19TH CONFERENCE ON DESIGN, AUTOMATION AND TEST IN EUROPE (DATE 2016), 2016
32016
Interaction of NoC design and Coherence Protocol in 3D-stacked CMPs
P Abad, P Prieto, LG Menezo, A Colaso, V Puente, JA Gregorio
2013 Euromicro Conference on Digital System Design, 48-55, 2013
22013
Topology-aware CMP design
P Prieto, V Puente, J Gregorio
Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC), 2009
22009
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation
A Colaso, P Prieto, JA Herrero, P Abad, V Puente, JA Gregorio
arXiv preprint arXiv:1902.02837, 2019
12019
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip
P Abad, P Prieto, V Puente, JA Gregorio
2012 IEEE 30th International Conference on Computer Design (ICCD), 55-60, 2012
12012
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