NBTI-aware data allocation strategies for scratchpad memory based embedded systems C Ferri, D Papagiannopoulou, RI Bahar, A Calimera 2011 12th Latin American Test Workshop (LATW), 1-6, 2011 | 26 | 2011 |
Playing with fire: Transactional memory revisited for error-resilient and energy-efficient MPSoC execution D Papagiannopoulou, A Marongiu, T Moreshet, L Benini, M Herlihy, ... Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 9-14, 2015 | 9 | 2015 |
Speculative synchronization for coherence-free embedded NUMA architectures D Papagiannopoulou, T Moreshet, A Marongiu, L Benini, M Herlihy, ... 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 9 | 2014 |
Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency D Papagiannopoulou, A Marongiu, T Moreshet, M Herlihy, R Bahar International Conference on Hardware/Software Co-design and System Synthesis …, 2017 | 7 | 2017 |
Flexible data allocation for scratch-pad memories to reduce NBTI effects D Papagiannopoulou, P Prasertsom, I Bahar International Symposium on Quality Electronic Design (ISQED), 60-67, 2013 | 6 | 2013 |
Evaluating critical bits in arithmetic operations due to timing violations S Whang, T Rachford, D Papagiannopoulou, T Moreshet, RI Bahar Design Automation Conference (DAC) - WiP, 2017 | 5 | 2017 |
Energy-efficient and high-performance lock speculation hardware for embedded multicore systems D Papagiannopoulou, G Capodanno, T Moreshet, M Herlihy, RI Bahar ACM Transactions on Embedded Computing Systems (TECS) 14 (3), 1-27, 2015 | 5 | 2015 |
IgnoreTM: Opportunistically ignoring timing violations for energy savings using HTM D Papagiannopoulou, S Whang, T Moreshet, RI Bahar 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 3 | 2019 |
NBTI-aware data allocation strategies for scratchpad based embedded systems C Ferri, D Papagiannopoulou, RI Bahar, A Calimera Journal of Electronic Testing 28 (3), 349-363, 2012 | 3 | 2012 |
Hardware Transactional Memory exploration in coherence-free many-core architectures D Papagiannopoulou, A Marongiu, T Moreshet, L Benini, M Herlihy, ... International Journal of Parallel Programming 46 (6), 1304-1328, 2018 | 2 | 2018 |
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems T Carle, D Papagiannopoulou, T Moreshet, A Marongiu, M Herlihy, ... Proceedings of the International Conference on Compilers, Architectures and …, 2016 | 2 | 2016 |
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs D Papagiannopoulou, RI Bahar, T Moreshet, M Herlihy, A Marongiu, ... Proceedings of the First International Workshop on Many-core Embedded …, 2013 | 2 | 2013 |
Embedded-SPEC: A Lightweight and Transparent Hardware Implementation of Lock Elision for Embedded Mulitcore Systems G Capodanno, D Papagiannopoulou, RI Bahar, T Moreshet, M Herlihy ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), 2013 | 2 | 2013 |
Opportunistically Ignoring Timing Violations for Energy Savings using HTM A Alkhatatbih, M Malekzadeh, T Moreshet, RI Bahar, ... Boston Area Architecture Workshop (BARC), 2020 | | 2020 |
Ignoring Timing Violations with Transactional Memory S Whang, D Papagiannopoulou, T Moreshet, RI Bahar Design Automation Conference (DAC), 2018 | | 2018 |
Thrifty-malloc: un gestionnaire dynamique de mémoire pour systèmes embarqués multicoeurs avec mémoire transactionnelle matérielle T Carle, D Papagiannopoulou, T Moreshet, A Marongiu, M Herlihy, ... Conférence d'informatique en Parallélisme, Architecture et Système (ComPAS …, 2017 | | 2017 |
A HTM-based mechanism for error-resilient and energy-efficient operation D Papagiannopoulou, A Marongiu, T Moreshet, M Herlihy, L Benini, ... Boston Area Architecture Workshop (BARC), 2016 | | 2016 |
Exploiting Transactional Memory for Error-Resilient and Energy-Efficient Operation D Papagiannopoulou, RI Bahar ACM Student Research Competition, International Conference On Computer Aided …, 2015 | | 2015 |
A transaction-friendly dynamic memory manager for embedded multicore systems T Carle, D Papagiannopoulou, I Bahar, M Herlihy, T Moreshet Workshop on the Theory of Transactional Memory (WTTM), 2015 | | 2015 |
Exploiting Hardware Transactional Memory for Error-Resilient and Energy-Efficient Execution D Papagiannopoulou, A Marongiu, T Moreshet, M Herlihy, L Benini, ... | | |