Prashant Nair
TitleCited byYear
AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
MK Qureshi, DH Kim, S Khan, PJ Nair, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
1432015
ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates
PJ Nair, DH Kim, MK Qureshi
ACM SIGARCH Computer Architecture News 41 (3), 72-83, 2013
1372013
Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
KK Chang, PJ Nair, D Lee, S Ghose, MK Qureshi, O Mutlu
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
1062016
DEUCE: Write-efficient encryption for non-volatile memories
V Young, PJ Nair, MK Qureshi
ACM SIGPLAN Notices 50 (4), 33-44, 2015
802015
A case for refresh pausing in DRAM memory systems
P Nair, CC Chou, MK Qureshi
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
802013
Architectural support for mitigating row hammering in DRAM memories
DH Kim, PJ Nair, MK Qureshi
IEEE Computer Architecture Letters 14 (1), 9-12, 2014
612014
Citadel: Efficiently protecting stacked memory from TSV and large granularity failures
PJ Nair, DA Roberts, MK Qureshi
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 49, 2016
372016
Reducing read latency of phase change memory via early read and turbo read
PJ Nair, C Chou, B Rajendran, MK Qureshi
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
362015
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability
PJ Nair, V Sridharan, MK Qureshi
Computer Architecture (ISCA), 2016 ACM/IEEE 43rd Annual International …, 2016
352016
Dice: Compressing dram caches for bandwidth and capacity
V Young, PJ Nair, MK Qureshi
2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture …, 2017
232017
Reducing refresh power in mobile devices with morphable ECC
C Chou, P Nair, MK Qureshi
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
232015
Refresh pausing in DRAM memory systems
PJ Nair, CC Chou, MK Qureshi
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 10, 2014
212014
F ault S im: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems
PJ Nair, DA Roberts, MK Qureshi
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 44, 2016
182016
FAULTSIM: A fast, configurable memory-resilience simulator
D Roberts, P Nair
The Memory Forum: In conjunction with ISCA 41, 2014
172014
Synergy: Rethinking secure-memory design for error-correcting memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, MK Qureshi
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
142018
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
G Saileshwar, P Nair, P Ramrakhyani, W Elsasser, J Joao, M Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
92018
Taming the instruction bandwidth of quantum computers via hardware-managed error correction
SS Tannu, ZA Myers, PJ Nair, DM Carmean, MK Qureshi
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017
82017
Attache: Towards ideal memory compression by mitigating metadata bandwidth overheads
S Hong, PJ Nair, B Abali, A Buyuktosunoglu, KH Kim, M Healy
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
72018
Memory page access detection
GH Loh, DA Roberts, MR Meswani, MR Nutter, JR Slice, P Nair, ...
US Patent 9,727,241, 2017
62017
SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM
PJ Nair, B Asgari, MK Qureshi
2019 49th Annual IEEE/IFIP International Conference on Dependable Systems …, 2019
12019
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Articles 1–20