Follow
Saeed Seyedfaraji
Saeed Seyedfaraji
Vienna University of Technology (TU Wien), Vienna, Austria
Verified email at tuwien.ac.at
Title
Cited by
Cited by
Year
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories
SS Faraji, J Talafy, AM Hajisadeghi, HR Zarandi
2018 21st Euromicro Conference on Digital System Design (DSD), 182-189, 2018
82018
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories
S Seyedfaraji, AM Hajisadeghi, J Talafy, HR Zarandi
Microprocessors and Microsystems 73, 102963, 2020
52020
EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit
S Seyedfaraji, JT Daryani, MMS Aly, S Rehman
IEEE Access 10, 82144-82155, 2022
42022
TAMPER: Thermal Assistant Method to Improve Write PERformance in STT-RAM Memories
SS Faraji, AM Hajisadeghi, H Zarandi
2019 27th Iranian Conference on Electrical Engineering (ICEE), 2039-2044, 2019
42019
AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator
S Seyedfaraji, B Mesgari, S Rehman
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 873-878, 2022
32022
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis
S Seyedfaraji, M Bichl, A Aftab, S Rehman
IEEE Access, 2024
2024
SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
S Seyedfaraji, B Mesgari, S Rehman
2022 25th Euromicro Conference on Digital System Design (DSD), 821-826, 2022
2022
The system can't perform the operation now. Try again later.
Articles 1–7