Joon Sohn
Joon Sohn
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Metal oxide-resistive memory using graphene-edge electrodes
S Lee, J Sohn, Z Jiang, HY Chen, HSP Wong
Nature communications 6 (1), 1-7, 2015
Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition
H Li, TF Wu, A Rahimi, KS Li, M Rusch, CH Lin, JL Hsu, MM Sabry, ...
2016 IEEE International Electron Devices Meeting (IEDM), 16.1. 1-16.1. 4, 2016
Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing
H Li, KS Li, CH Lin, JL Hsu, WC Chiu, MC Chen, TT Wu, J Sohn, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
HY Chen, S Brivio, CC Chang, J Frascaroli, TH Hou, B Hudec, M Liu, H Lv, ...
Journal of Electroceramics 39 (1), 21-38, 2017
Hysteresis-free carbon nanotube field-effect transistors
RS Park, G Hills, J Sohn, S Mitra, MM Shulaker, HSP Wong
ACS nano 11 (5), 4785-4791, 2017
All-metal-nitride RRAM devices
Z Zhang, B Gao, Z Fang, X Wang, Y Tang, J Sohn, HSP Wong, SS Wong, ...
IEEE Electron Device Letters 36 (1), 29-31, 2014
The Role of Ti Capping Layer in HfOx-Based RRAM Devices
Z Fang, XP Wang, J Sohn, BB Weng, ZP Zhang, ZX Chen, YZ Tang, ...
IEEE Electron Device Letters 35 (9), 912-914, 2014
Ultrathin (∼2nm) HfOxas the fundamental resistive switching element: Thickness scaling limit, stack engineering and 3D integration
L Zhao, Z Jiang, HY Chen, J Sohn, K Okabe, B Magyari-Köpe, HSP Wong, ...
2014 IEEE International Electron Devices Meeting, 6.6. 1-6.6. 4, 2014
Phonon conduction in silicon nanobeam labyrinths
W Park, G Romano, EC Ahn, T Kodama, J Park, MT Barako, J Sohn, ...
Scientific reports 7 (1), 1-7, 2017
Atomically thin graphene plane electrode for 3D RRAM
J Sohn, S Lee, Z Jiang, HY Chen, HSP Wong
2014 IEEE International Electron Devices Meeting, 5.3. 1-5.3. 4, 2014
Error-resilient analog image storage and compression with analog-valued RRAM arrays: an adaptive joint source-channel coding approach
X Zheng, R Zarcone, D Paiton, J Sohn, W Wan, B Olshausen, HSP Wong
2018 IEEE International Electron Devices Meeting (IEDM), 3.5. 1-3.5. 4, 2018
First demonstration of RRAM patterned by block copolymer self-assembly
Y Wu, H Yi, Z Zhang, Z Jiang, J Sohn, S Wong, HSP Wong
2013 IEEE International Electron Devices Meeting, 20.8. 1-20.8. 4, 2013
Impact of thermally dead volume on phonon conduction along silicon nanoladders
W Park, J Sohn, G Romano, T Kodama, A Sood, JS Katz, BSY Kim, H So, ...
Nanoscale 10 (23), 11117-11122, 2018
One-step fabrication of optically transparent polydimethylsiloxane artificial lotus leaf film using under-exposed under-baked photoresist mold
Y Yoon, DW Lee, JH Ahn, J Sohn, JB Lee
2012 IEEE 25th International Conference on Micro Electro Mechanical Systems …, 2012
IEEE Symp. VLSI Technol
H Li, KS Li, CH Lin, JL Hsu, WC Chiu, MC Chen, TT Wu, J Sohn, ...
IEEE, Piscataway, NJ, 1-2, 2016
graphene plane electrode for low power 3d resistive random access memory
S Lee, J Sohn, Z Jiang, HY Chen, HSP Wong
ECS Transactions 72 (4), 159, 2016
Graphene-based 3D XNOR-VRRAM with ternary precision for neuromorphic computing
B Alimkhanuly, J Sohn, IJ Chang, S Lee
npj 2D Materials and Applications 5 (1), 1-10, 2021
Resistive Switching Random Access Memory-Device Scaling in 3D Architecture and Integration with Complementary Metal Oxide Semiconductor
J Sohn
Stanford University, 2018
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