Robert J Halstead
Robert J Halstead
Correu electrònic verificat a
Citada per
Citada per
Designing modular hardware accelerators in C with ROCCC 2.0
J Villarreal, A Park, W Najjar, R Halstead
2010 18th IEEE annual international symposium on field-programmable custom …, 2010
High-level language tools for reconfigurable computing
S Windh, X Ma, RJ Halstead, P Budhkar, Z Luna, O Hussaini, WA Najjar
Proceedings of the IEEE 103 (3), 390-408, 2015
Accelerating join operation for relational databases with FPGAs
RJ Halstead, B Sukhwani, H Min, M Thoennes, P Dube, S Asaad, B Iyer
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013
FPGA-based Multithreading for In-Memory Hash Joins.
RJ Halstead, I Absalyamov, WA Najjar, VJ Tsotras
CIDR, 2015
Exploring irregular memory accesses on fpgas
RJ Halstead, J Villarreal, W Najjar
Proceedings of the 1st Workshop on Irregular Applications: Architectures and …, 2011
Efficient XML Path Filtering Using GPUs.
R Moussalli, RJ Halstead, M Salloum, WA Najjar, VJ Tsotras
ADMS@ VLDB, 9-18, 2011
Compiled multithreaded data paths on fpgas for dynamic workloads
RJ Halstead, W Najjar
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
Compiling irregular applications for reconfigurable systems
RJ Halstead, J Villarreal, WA Najjar
International Journal of High Performance Computing and Networking 7 (4 …, 2014
FPGA-accelerated group-by aggregation using synchronizing caches
I Absalyamov, P Budhkar, S Windh, RJ Halstead, WA Najjar, VJ Tsotras
Proceedings of the 12th International Workshop on Data Management on New …, 2016
A study on parallelizing XML path filtering using accelerators
R Moussalli, M Salloum, R Halstead, W Najjar, VJ Tsotras
ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-28, 2014
Using Multithreaded Techniques to Mask Memory Latency on FPGA Accelerators
RJ Halstead
University of California, Riverside, 2015
WA Najjar, J Villarreal, RJ Halstead
FPGAs for Software Programmers, 191-204, 2016
SpVM acceleration with latency masking threads on FPGAs
RJ Halstead, WA Najjar, O Huseini
algorithms 20, 21, 2014
Is there a tradeoff between programmability and performance?
R Halstead, J Villarreal, R Moussalli, W Najjar
2010 Conference Record of the Forty Fourth Asilomar Conference on Signals …, 2010
Efficient local locking for massively multithreaded in-memory hash-based operators
B Romanous, S Windh, I Absalyamov, P Budhkar, R Halstead, W Najjar, ...
The VLDB Journal 30 (3), 333-359, 2021
Data filtering using a plurality of hardware accelerators
SW Asaad, RJ Halstead, B Sukhwani
US Patent 10,387,403, 2019
Special Issue on Reconfigurable Systems: Foundations [Guest editors' introduction]
J Lyke, CG Christodoulou, A Vera, AH Edwards
Proceedings of the IEEE 103 (3), 287-290, 2015
Data filtering using a plurality of hardware accelerators
S Asaad, RJ Halstead, B Sukhwani
US Patent App. 16/412,626, 2019
Data filtering using a plurality of hardware accelerators
SW Asaad, RJ Halstead, B Sukhwani
US Patent 10,372,700, 2019
High Level Language Tools for Reconfigurable Computing
R Halstead, P Budhkar, O Hussaini, Z Luna
En aquests moments el sistema no pot dur a terme l'operació. Torneu-ho a provar més tard.
Articles 1–20