VLSI physical design: from graph partitioning to timing closure AB Kahng, J Lienig, IL Markov, J Hu Springer, 2011 | 485 | 2011 |
Vicis: A reliable network for unreliable silicon D Fick, A DeOrio, J Hu, V Bertacco, D Blaauw, D Sylvester Proceedings of the 46th Annual Design Automation Conference, 812-817, 2009 | 246 | 2009 |
Progress and challenges in VLSI placement research IL Markov, J Hu, MC Kim Proceedings of the International Conference on Computer-Aided Design, 275-282, 2012 | 172 | 2012 |
A reliable routing architecture and algorithm for NoCs A DeOrio, D Fick, V Bertacco, D Sylvester, D Blaauw, J Hu, G Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 132 | 2012 |
A SimPLR method for routability-driven placement MC Kim, J Hu, DJ Lee, IL Markov 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 67-73, 2011 | 122 | 2011 |
ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite MC Kim, J Hu, J Li, N Viswanathan 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 921-926, 2015 | 91 | 2015 |
Completing high-quality global routes J Hu, JA Roy, IL Markov Proceedings of the 19th international symposium on Physical design, 35-41, 2010 | 85 | 2010 |
Sensitivity-guided metaheuristics for accurate discrete gate sizing J Hu, AB Kahng, SH Kang, MC Kim, IL Markov Proceedings of the International Conference on Computer-Aided Design, 233-239, 2012 | 80 | 2012 |
Sidewinder: a scalable ILP-based router J Hu, JA Roy, IL Markov Proceedings of the 2008 international workshop on System level interconnect …, 2008 | 34 | 2008 |
TAU 2015 contest on incremental timing analysis J Hu, G Schaeffer, V Garg 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 882-889, 2015 | 33 | 2015 |
TAU 2014 contest on removing common path pessimism during timing analysis J Hu, D Sinha, I Keller Proceedings of the 2014 on International Symposium on physical design, 153-160, 2014 | 29 | 2014 |
Taming the complexity of coordinated place and route J Hu, MC Kim, IL Markov Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013 | 20 | 2013 |
Global and detailed placement AB Kahng, J Lienig, IL Markov, J Hu VLSI Physical Design: From Graph Partitioning to Timing Closure, 95-130, 2022 | 7 | 2022 |
Timing closure AB Kahng, J Lienig, IL Markov, J Hu, AB Kahng, J Lienig, IL Markov, J Hu VLSI Physical Design: From Graph Partitioning to Timing Closure, 219-264, 2011 | 5 | 2011 |
TAU 2014 contest on removing common path pessimism during timing analysis: Special session paper: Common path pessimism removal (CPPR) J Hu, D Sinha, I Keller 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 591-591, 2014 | 4 | 2014 |
Statistical timing using macro-model considering statistical timing value entry J Hu, SSK Raghunathan, D Sinha, VP Zolotov US Patent 9,798,843, 2017 | 3 | 2017 |
High-performance Global Routing for Trillion-gate Systems-on-Chips. J Hu | 3 | 2013 |
Netlist and system partitioning AB Kahng, J Lienig, IL Markov, J Hu, AB Kahng, J Lienig, IL Markov, J Hu VLSI Physical Design: From Graph Partitioning to Timing Closure, 31-54, 2011 | 3 | 2011 |
Chip Planning AB Kahng, J Lienig, IL Markov, J Hu, AB Kahng, J Lienig, IL Markov, J Hu VLSI Physical Design: From Graph Partitioning to Timing Closure, 55-92, 2011 | 2 | 2011 |
Routing GE Téllez, J Hu, Y Wei Electronic Design Automation for IC Implementation, Circuit Design, and …, 2017 | 1 | 2017 |