Vinícius Dal Bem
Vinícius Dal Bem
Verified email at inf.ufrgs.br
TitleCited byYear
Transistor network restructuring against NBTI degradation
PF Butzen, V Dal Bem, AI Reis, RP Ribas
Microelectronics Reliability 50 (9-11), 1298-1303, 2010
162010
Design of CMOS logic gates with enhanced robustness against aging degradation
PF Butzen, V Dal Bem, AI Reis, RP Ribas
Microelectronics Reliability 52 (9-10), 1822-1826, 2012
142012
Impact and optimization of lithography-aware regular layout in digital circuit design
V Dal Bem, P Butzen, FS Marranghello, AI Reis, RP Ribas
2011 IEEE 29th International Conference on Computer Design (ICCD), 279-284, 2011
112011
BTI and HCI first-order aging estimation for early use in standard cell technology mapping
PF Butzen, V Dal Bem, AI Reis, RP Ribas
Microelectronics Reliability 53 (9-11), 1360-1364, 2013
52013
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
V Dal Bem, PF Butzen, CE Klock, V Callegaro, AI Reis, RP Ribas
Proceedings of the 24th symposium on Integrated circuits and systems design …, 2011
32011
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC
V Dal Bem, FS Marranghello, AI Reis, RP Ribas
IEEE Transactions on Emerging Topics in Computing 5 (2), 247-259, 2016
12016
Logic synthesis for manufacturability considering regularity and lithography printability
L Machado, V Dal Bem, F Moll, S Gómez, RP Ribas, AI Reis
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 230-235, 2013
12013
Lithography analysis of via-configurable transistor-array fabrics
V Dal Bem, AI Reis, RP Ribas
NORCHIP 2012, 1-4, 2012
12012
Transistor sizing in lithography-aware regular fabrics
FS Marranghello, V Dal Bem, AI Reis, F Moll, RP Ribas
Proceedings of the 24th symposium on Integrated circuits and systems design …, 2011
12011
Efeitos Físicos Nanométricos em Circuitos Inte-grados Digitais
PF Butzen, V Dal Bem, L da Rosa Jr, AI Reis, RP Ribas
Pelotas: Universidade Federal de Pelotas, 2009
12009
SAT based environment for logical capacity evaluation of via configurable block templates
V Dal Bem
2016
Analytical logical effort formulation for minimum active area under delay constraints
CGP Alegretti, V Dal Bem, RP Ribas, AI Reis
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
2013
23rd European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis
M Ciappa, P Cova, F Iannuzzo, G Meneghesso
Microelectronics Reliability, Special Issue 52 (9-10), 1751-2512, 2012
2012
Transistor sizing analysis of regular fabrics
FS Marranghello, V Dal Bem, AI Reis, RP Ribas, FB Moll Echeto
1st Workshop on Exploiting Regularity in the Design of IPs, Architectures …, 2011
2011
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits
PF Butzen, VD Bem, AI Reis, RP Ribas
Journal of Low Power Electronics 6 (1), 192-200, 2010
2010
CMOS digital integrated circuit design faced to NBTI and other nanometric effects
V Dal Bem
2010
Equivalent Circuit for NBTI Evaluation in CMOS Logic Gates
N Schuch, V Dal Bem, AI Reis, RP Ribas
ECS Transactions 23 (1), 421-428, 2009
2009
Challenges for Optimization of Transistors Array-based Via-Configurable Regular Layout
V Dal Bem, AI Reis, RP Ribas
Explicit Logical Effort Formulation for Minimum Active Area under Delay Constraints
CGP Alegretti, V Dal Bem, RP Ribas, AI Reis
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