Ramon Canal
TitleCited byYear
Dynamic cluster assignment mechanisms
R Canal, JM Parcerisa, A González
Proceedings Sixth International Symposium on High-Performance Computer …, 2000
1562000
Very low power pipelines using significance compression
R Canal, A González, JE Smith
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
1542000
A low-complexity issue logic
R Canal, A González
Proceedings of the 14th international conference on Supercomputing, 327-335, 2000
1222000
Process variation tolerant 3T1D-based cache architectures
X Liang, R Canal, GY Wei, D Brooks
Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007
1182007
Design space exploration for multicore architectures: a power/performance/thermal view
M Monchiero, R Canal, A González
Proceedings of the 20th annual international conference on Supercomputing …, 2006
1142006
Power/performance/thermal design-space exploration for multicore architectures
M Monchiero, R Canal, A Gonzalez
IEEE Transactions on Parallel and Distributed Systems 19 (5), 666-681, 2008
862008
A cost-effective clustered architecture
R Canal, JM Parcerisa, A Gonzalez
1999 International Conference on Parallel Architectures and Compilation …, 1999
791999
Reducing the complexity of the issue logic
R Canal, A González
Proceedings of the 15th international conference on Supercomputing, 312-320, 2001
772001
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
E Herrero, J González, R Canal
ACM SIGARCH Computer Architecture News 38 (3), 419-428, 2010
732010
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
N Jing, Y Shen, Y Lu, S Ganapathy, Z Mao, M Guo, R Canal, X Liang
ACM SIGARCH Computer Architecture News 41 (3), 344-355, 2013
652013
Distributed cooperative caching
E Herrero, J González, R Canal
2008 International Conference on Parallel Architectures and Compilation …, 2008
632008
Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
X Liang, R Canal, GY Wei, D Brooks
IEEE micro 28 (1), 60-68, 2008
502008
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
A Valero, J Sahuquillo, S Petit, V Lorente, R Canal, P López, J Duato
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
482009
Power-and complexity-aware issue queue designs
J Abella Ferrer, R Canal Corretger, AM González Colás
IEEE micro 23 (5), 50-58, 2003
382003
Dynamic code partitioning for clustered architectures
R Canal, JM Parcerisa, A González
International Journal of Parallel Programming 29 (1), 59-79, 2001
302001
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
S Ganapathy, R Canal, A Gonzalez, A Rubio
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
272010
Software-controlled operand-gating
R Canal, A González, JE Smith
International Symposium on Code Generation and Optimization, 2004. CGO 2004 …, 2004
252004
Distributed cooperative caching: An energy efficient memory scheme for chip multiprocessors
E Herrero, J Gonzalez, R Canal
IEEE Transactions on Parallel and Distributed Systems 23 (5), 853-861, 2011
202011
Merlin: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment
M Kaliorakis, D Gizopoulos, R Canal, A Gonzalez
ACM SIGARCH Computer Architecture News 45 (2), 241-254, 2017
182017
A detailed methodology to compute soft error rates in advanced technologies
M Riera, R Canal, J Abella, A Gonzalez
Proceedings of the 2016 Conference on Design, Automation & Test in Europe …, 2016
162016
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