RAIDR: Retention-aware intelligent DRAM refresh J Liu, B Jaiyen, R Veras, O Mutlu ACM SIGARCH Computer Architecture News 40 (3), 1-12, 2012 | 506 | 2012 |

A stencil compiler for short-vector SIMD architectures T Henretty, R Veras, F Franchetti, LN Pouchet, J Ramanujam, ... Proceedings of the 27th international ACM conference on International …, 2013 | 148 | 2013 |

When polyhedral transformations meet SIMD code generation M Kong, R Veras, K Stock, F Franchetti, LN Pouchet, P Sadayappan Proceedings of the 34th ACM SIGPLAN conference on Programming language …, 2013 | 136 | 2013 |

SPIRAL: Extreme performance portability F Franchetti, TM Low, DT Popovici, RM Veras, DG Spampinato, ... Proceedings of the IEEE 106 (11), 1935-1968, 2018 | 40 | 2018 |

FLAMES2S: From abstraction to high performance R Veras, J Monette, R Van de Geijn, ES Quintana-Ortí Computer Science Department, University of Texas at Austin, 2008 | 8 | 2008 |

Compilers, hands-off my hands-on optimizations R Veras, DT Popovici, TM Low, F Franchetti Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector …, 2016 | 7 | 2016 |

Capturing the expert: Generating fast matrix-multiply kernels with spiral R Veras, F Franchetti International Conference on High Performance Computing for Computational …, 2014 | 6 | 2014 |

Automating the Last-Mile for High Performance Dense Linear Algebra RM Veras, TM Low, TM Smith, RA van de Geijn, F Franchetti ArXiv e-prints, 2016 | 5 | 2016 |

A Scale-Free Structure for Power-Law Graphs RM Veras, TM Low, F Franchetti High Performance Extreme Computing Conference (HPEC), 2016 IEEE, 2016 | 5 | 2016 |

Transforming linear algebra libraries: From abstraction to high performance RM Veras, JS Monette, ES Quintana-Ort, RA van de Geijn ACM Trans. Math. Soft, 0 | 3 | |

Analytical cache modeling and tilesize optimization for tensor contractions R Li, A Sukumaran-Rajam, R Veras, TM Low, F Rastello, A Rountev, ... Proceedings of the International Conference for High Performance Computing …, 2019 | 2 | 2019 |

A domain-specific language and compiler for stencil computations on short-vector simd and gpu architectures T Henretty, J Holewinski, R Veras, F Franchetti, LN Pouchet, ... | 2 | |

From High-Level Specification to High-Performance Code Z Wang, M O’Boyle, PS Rawat, M Vaidya, A Sukumaran-Rajam, ... Proceedings of the IEEE 106 (11), 2018 | | 2018 |

A scale-free structure for real world networks RM Veras, F Franchetti 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | | 2017 |

A Systematic Approach for Obtaining Performance on Matrix-Like Operations RM Veras Carnegie Mellon University, 2017 | | 2017 |

Aggressive Scheduling for Numerical Programs R Veras, F Cruz, B Akin | | 2012 |

RAIDR: Reten on‐Aware Intelligent DRAM Refresh J Liu, B Jaiyen, R Veras, O Mutlu | | |

Session 2A: GPU Architectures J Liu, B Jaiyen, RM Veras, O Mutlu, MN Bojnordi, E Ipek, DH Yoon, ... | | |