| Automated design of error-resilient and hardware-efficient deep neural networks C Schorn, T Elsken, S Vogel, A Runge, A Guntoro, G Ascheid Neural Computing and Applications 32, 18327-18345, 2020 | 46 | 2020 |
| Precise self-calibration of ultrasound based indoor localization systems A Runge, M Baunach, R Kolla 2011 International Conference on Indoor Positioning and Indoor Navigation, 1-8, 2011 | 29 | 2011 |
| FaFNoC: A Fault-tolerant and Bufferless Network-on-chip A Runge Procedia computer science 56, 397-402, 2015 | 19 | 2015 |
| Fault-tolerant network-on-chip based on fault-aware flits and deflection routing A Runge Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015 | 17 | 2015 |
| Reliability enhancement of fault-prone many-core systems combining spatial and temporal redundancy A Runge 2012 IEEE 14th International Conference on High Performance Computing and …, 2012 | 6 | 2012 |
| Using Benes Networks at Fault-tolerant and Deflection Routing based Network-on-Chips A Runge, R Kolla 10th IEEE/ACM International Symposium on Network-on-Chip (NOCS 2016), 1-8, 2016 | 3 | 2016 |
| Consideration of the flit size for deflection routing based network-on-chips A Runge, R Kolla Proceedings of the 1st International Workshop on Advanced Interconnect …, 2016 | 3 | 2016 |
| Determination of the optimum degree of redundancy for fault-prone many-core systems A Runge GMM-Fachbericht-Zuverlässigkeit und Entwurf, 2012 | 2 | 2012 |
| Method and device for verifying a neuron function in a neural network A Guntoro, A Runge, C Schorn, S Vogel, J Topp, J Schirmer US Patent 11,593,232, 2023 | 1 | 2023 |
| Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators T Soliman, A Runge, L Ecco 2020 IEEE International Parallel and Distributed Processing Symposium …, 2020 | 1 | 2020 |
| Device and computer-implemented method for a neural architecture search A Runge, D Oshinubi, F Rehm, M Meixner, M Klaiber US Patent App. 18/002,305, 2023 | | 2023 |
| Method and device for operating a neural network in a memory-efficient manner A Guntoro, A Runge, C Schorn, J Topp, S Vogel, J Schirmer US Patent 11,715,019, 2023 | | 2023 |
| Selective deactivation of processing units for artificial neural networks J Schirmer, A Guntoro, A Runge, C Schorn, J Topp, S Vogel US Patent 11,698,672, 2023 | | 2023 |
| Best of both, Structured and Unstructured Sparsity in Neural Networks C Schulte, S Wagner, A Runge, D Bariamis, B Hammer 3rd Workshop on Machine Learning and Systems (EuroMLSys ’23), 5, 2023 | | 2023 |
| Device and method for providing classified digital recordings for a system for automatic machine learning and for updating a machine-readable program code therewith A Runge, C Weiss, G Hakobyan, S Leidich US Patent App. 17/854,931, 2023 | | 2023 |
| Device, memory medium, computer program and computer-implemented method for validating a data-based model A Runge, C Weiss, G Hakobyan, S Leidich US Patent App. 17/854,722, 2023 | | 2023 |
| Device and method for processing data of a neural network A Runge, T Wenzel US Patent App. 17/762,954, 2022 | | 2022 |
| Bosch Deep Learning Hardware Benchmark A Runge, T Wenzel, D Bariamis, BS Staffler, LR Drumond, M Pfeiffer arXiv preprint arXiv:2008.10293, 2020 | | 2020 |
| TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips A Runge, R Kolla Journal of Systems Architecture 75, 145-154, 2017 | | 2017 |
| Advances in Deflection Routing Based Network on Chips: Fortschritte Bei Deflection Routing Basierten Network on Chips A Runge Julius-Maximilians-Universität Würzburg, 2017 | | 2017 |
