| Design and analysis of harmonic rejection mixers with programmable LO frequency T Forbes, WG Ho, R Gharpurey IEEE Journal of Solid-State Circuits 48 (10), 2363-2374, 2013 | 79 | 2013 |
| A 2 GS/s frequency-folded ADC-based broadband sampling receiver T Forbes, R Gharpurey IEEE Journal of Solid-State Circuits 49 (9), 1971-1983, 2014 | 36 | 2014 |
| A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection V Singh, T Forbes, WG Ho, J Ko, R Gharpurey Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 18 | 2014 |
| Techniques for dynamic range enhancement in a frequency-folded broadband channelizer WG Ho, V Singh, T Forbes, R Gharpurey 2014 IEEE Dallas Circuits and Systems Conference (DCAS), 1-4, 2014 | 11 | 2014 |
| A 2-stage recursive receiver optimized for low flicker noise corner R Srinivasan, WG Ho, T Forbes, R Gharpurey 2014 IEEE Radio Frequency Integrated Circuits Symposium, 47-50, 2014 | 11 | 2014 |
| An active interference cancellation technique with harmonic rejection for a broadband channelizer WG Ho, T Forbes, V Singh, R Gharpurey 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 10 | 2013 |
| Circuit techniques for programmable broadband radio receivers TM Forbes | 8 | 2013 |
| Embedded LO synthesis method in harmonic rejection mixers T Forbes, R Gharpurey 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 7 | 2012 |
| A frequency-folded ADC architecture with digital LO synthesis T Forbes, WG Ho, N Sun, R Gharpurey 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 149-152, 2013 | 6 | 2013 |
| A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm Area Efficiency T Forbes, B Magstadt, J Moody, J Saugen, A Suchanek, S Nelson IEEE Journal of Solid-State Circuits, 2023 | 5 | 2023 |
| A 67 GHz 23 mW Receiver Utilizing Complementary Current Reuse Techniques J Moody, S Lepkowski, T Forbes 2022 17th European Microwave Integrated Circuits Conference (EuMIC), 292-295, 2022 | 5 | 2022 |
| A 0.2-2 GHz Time-Interleaved Multi-Stage Switched-Capacitor Delay Element Achieving 448.6 ns Delay and 330 ns/mm2 Area Efficiency T Forbes, B Magstadt, J Moody, A Suchanek, S Nelson 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 135-138, 2022 | 5 | 2022 |
| Circuit techniques for the rejection of LO harmonics within CMOS Mixers TM Forbes | 4 | 2012 |
| Programmable delay device enabling large delay in small package T Forbes, J Moody, BT Magstadt US Patent 11,683,023, 2023 | 2 | 2023 |
| A low-power two-stage harmonic rejection quadrature mixer employing bias-current reuse WG Ho, T Forbes, R Gharpurey 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 2 | 2015 |
| An active interference canceler with reduced harmonic response and synthesizer tuning range WG Ho, V Singh, T Forbes, R Gharpurey 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 383-386, 2015 | 2 | 2015 |
| A Low Power V-Band LNA with Wide Supply Voltage Range Exploiting Complementary Current Reuse and Power Efficient Bias Point J Moody, S Lepkowski, TM Forbes 2023 IEEE/MTT-S International Microwave Symposium-IMS 2023, 135-138, 2023 | 1 | 2023 |
| Differential Cancellation Based RF Switch Enabling High Isolation and Minimal Insertion Loss in 0.0006 mm2 Area T Forbes, J Saugen, B Magstadt 2022 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems …, 2022 | 1 | 2022 |
| A mmW Receiver Exploiting Complementary Current Reuse and Power Efficient Bias Point J Moody, S Lepkowski, T Forbes IEEE Transactions on Microwave Theory and Techniques, 2023 | | 2023 |
| A 0.2-2 GHz RF Delay Element Achieving 2.55-448.6 ns Programmable Delay Range T Forbes, B Magstadt, J Moody, J Saugen, A Suchanek, S Nelson GOMAC 2023, 2023 | | 2023 |
Jesse MoodySandia National laboratoryVerified email at sandia.gov
