Hao Cai
Hao Cai
MdC@TELECOM Paris, Southeast University, Nanjing, China
Dirección de correo verificada de telecom-paristech.fr
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Compact model of dielectric breakdown in spin-transfer torque magnetic tunnel junction
Y Wang, H Cai, LA de Barros Naviner, Y Zhang, X Zhao, E Deng, JO Klein, ...
IEEE Transactions on Electron Devices 63 (4), 1762-1767, 2016
642016
Robust ultra-low power non-volatile logic-in-memory circuits in FD-SOI technology
H Cai, Y Wang, LADB Naviner, W Zhao
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (4), 847-857, 2016
542016
A review of sparse recovery algorithms
EC Marques, N Maciel, L Naviner, H Cai, J Yang
IEEE Access 7, 1300-1322, 2018
522018
Multiplexing sense-amplifier-based magnetic flip-flop in a 28-nm FDSOI technology
H Cai, Y Wang, W Zhao, LA de Barros Naviner
IEEE Transactions on Nanotechnology 14 (4), 761-767, 2015
332015
A novel circuit design of true random number generator using magnetic tunnel junction
Y Wang, H Cai, LAB Naviner, JO Klein, J Yang, W Zhao
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
302016
High performance MRAM with spin-transfer-torque and voltage-controlled magnetic anisotropy effects
H Cai, W Kang, Y Wang, LADB Naviner, J Yang, W Zhao
Applied Sciences 7 (9), 929, 2017
272017
Compact thermal modeling of spin transfer torque magnetic tunnel junction
Y Wang, H Cai, LAB Naviner, Y Zhang, JO Klein, WS Zhao
Microelectronics Reliability 55 (9-10), 1649-1653, 2015
262015
Reliability aware design of low power continuous-time sigma–delta modulator
H Cai, H Petit, JF Naviner
Microelectronics Reliability 51 (9-11), 1449-1453, 2011
222011
A hierarchical reliability simulation methodology for AMS integrated circuits and systems
H Cai, H Petit, JF Naviner
Journal of Low Power Electronics 8 (5), 697-705, 2012
212012
Stochastic computation with spin torque transfer magnetic tunnel junction
LA de Barros Naviner, H Cai, Y Wang, W Zhao, AB Dhia
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
202015
A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology
K Liu, T An, H Cai, L Naviner, JF Naviner, H Petit
Eurocon 2013, 1829-1836, 2013
172013
Breakdown Analysis of Magnetic Flip-flop With 28nm UTBB FDSOI Technology
CAI Hao, Y Wang, L Naviner, W Zhao
IEEE Transactions on Device and Materials Reliability 16 (3), 376-383, 2016
132016
Low power magnetic flip-flop optimization with FDSOI technology boost
H Cai, Y Wang, LA de Barros Naviner, W Zhao
IEEE Transactions on Magnetics 52 (8), 1-7, 2016
132016
Exploring hybrid STT-MTJ/CMOS energy solution in near-/sub-threshold regime for IoT applications
H Cai, Y Wang, LA de Barros Naviner, J Yang, W Zhao
IEEE Transactions on magnetics 54 (2), 1-9, 2017
112017
Approximate computing in MOS/spintronic non-volatile full-adder
H Cai, Y Wang, LAB Naviner, Z Wang, W Zhao
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
92016
A statistical method for transistor ageing and process variation applied to reliability simulation
H Cai, H Petit, JF Naviner
3rd European Workshop on CMOS variability, 49–52, 2012
82012
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM
Y Zhou, H Cai, L Xie, M Han, M Liu, S Xu, B Liu, W Zhao, J Yang
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (5), 1602-1614, 2020
72020
Efficient reliability evaluation methodologies for combinational circuits
H Cai, K Liu, LA de Barros Naviner, Y Wang, M Slimani, JF Naviner
Microelectronics Reliability 64, 19-25, 2016
72016
Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method
T An, K Liu, H Cai, LAB Naviner
Microelectronics Reliability 55 (3-4), 696-703, 2015
72015
A high-reliability and low-power computing-in-memory implementation within STT-MRAM
L Zhang, E Deng, H Cai, Y Wang, L Torres, A Todri-Sanial, Y Zhang
Microelectronics Journal 81, 69-75, 2018
62018
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Artículos 1–20