Tushar Krishna
Tushar Krishna
Assistant Professor, Georgia Tech
Verified email at ece.gatech.edu - Homepage
Cited by
Cited by
The gem5 simulator
N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ...
ACM SIGARCH Computer Architecture News 39 (2), 1-7, 2011
Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
YH Chen, T Krishna, JS Emer, V Sze
IEEE journal of solid-state circuits 52 (1), 127-138, 2016
GARNET: A detailed on-chip network model inside a full-system simulator
N Agarwal, T Krishna, LS Peh, NK Jha
2009 IEEE international symposium on performance analysis of systems and …, 2009
SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
BK Daya, CHO Chen, S Subramanian, WC Kwon, S Park, T Krishna, ...
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
Breaking the on-chip latency barrier using SMART
T Krishna, CHO Chen, WC Kwon, LS Peh
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
S Park, T Krishna, CH Chen, B Daya, A Chandrakasan, LS Peh
Proceedings of the 49th Annual Design Automation Conference, 398-405, 2012
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Programmable Interconnects
H Kwon, A Samajdar, T Krishna
Proceedings of the International Conference on Architectural Support for …, 2018
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
T Krishna, LS Peh, BM Beckmann, SK Reinhardt
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
NoC with near-ideal express virtual channels using global-line communication
T Krishna, A Kumar, P Chiang, M Erez, LS Peh
2008 16th IEEE Symposium on High Performance Interconnects, 11-20, 2008
SMART: A single-cycle reconfigurable NoC for SoC applications
CHO Chen, S Park, T Krishna, S Subramanian, AP Chandrakasan, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 338-343, 2013
Scale-sim: Systolic cnn accelerator simulator
A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883, 2018
Swift: A swing-reduced interconnect for a token-based network-on-chip in 90nm cmos
T Krishna, J Postman, C Edmonds, LS Peh, P Chiang
2010 IEEE International Conference on Computer Design, 439-446, 2010
Message broadcast with router bypassing
T Krishna, BM Beckmann, SK Reinhardt
US Patent 9,015,448, 2015
SMART: single-cycle multihop traversals over a shared network on chip
T Krishna, CHO Chen, WC Kwon, LS Peh
IEEE micro 34 (3), 43-56, 2014
Swift: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects
J Postman, T Krishna, C Edmonds, LS Peh, P Chiang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (8 …, 2012
On-chip networks
NE Jerger, T Krishna, LS Peh
Synthesis Lectures on Computer Architecture 12 (3), 1-210, 2017
Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach
H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
Express virtual channels with capacitively driven global links
T Krishna, A Kumar, LS Peh, J Postman, P Chiang, M Erez
Micro, IEEE 29 (4), 48-61, 2009
Efficient control and communication paradigms for coarse-grained spatial architectures
M Pellauer, A Parashar, M Adler, B Ahsan, R Allmon, N Crago, K Fleming, ...
ACM Transactions on Computer Systems (TOCS) 33 (3), 1-32, 2015
Single-cycle collective communication over a shared network fabric
T Krishna, LS Peh
2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 1-8, 2014
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