Stefan Metzlaff
Stefan Metzlaff
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TítuloCitado porAño
Merasa: Multicore execution of hard real-time applications supporting analyzability
T Ungerer, F Cazorla, P Sainrat, G Bernat, Z Petrov, C Rochange, ...
IEEE Micro 30 (5), 66-75, 2010
1752010
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors
S Metzlaff, S Uhrig, J Mische, T Ungerer
Proceedings of the 9th workshop on MEmory performance: DEaling with …, 2008
382008
RTOS support for parallel execution of hard real-time applications on the MERASA multi-core processor
J Wolf, M Gerdes, F Kluge, S Uhrig, J Mische, S Metzlaff, C Rochange, ...
2010 13th IEEE International Symposium on Object/Component/Service-Oriented …, 2010
372010
A dynamic instruction scratchpad memory for embedded processors managed by hardware
S Metzlaff, I Guliashvili, S Uhrig, T Ungerer
International Conference on Architecture of Computing Systems, 122-134, 2011
332011
A hard real-time capable multi-core SMT processor
M Paolieri, J Mische, S Metzlaff, M Gerdes, E Quiñones, S Uhrig, ...
ACM Transactions on Embedded Computing Systems (TECS) 12 (3), 79, 2013
282013
A Real-Time Capable Many-Core Model
S Metzlaff, J Mische, T Ungerer
RTSS 2011: Work-in-Progress Session, 21-24, 2011
242011
Impact of instruction cache and different instruction scratchpads on the wcet estimate
S Metzlaff, T Ungerer
2012 IEEE 14th International Conference on High Performance Computing and …, 2012
82012
Exploiting Intel TSX for fault-tolerant execution in safety-critical systems
F Haas, S Weis, S Metzlaff, T Ungerer
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2014
62014
A comparison of instruction memories from the WCET perspective
S Metzlaff, T Ungerer
Journal of Systems Architecture 60 (5), 452-466, 2014
52014
Distributed memory on chip–bringing together low power and real-time
J Mische, S Metzlaff, T Ungerer
Proceedings of the Workshop on Reconciling Performance and Predictability (RePP), 2014
52014
Replacement policies for a function-based instruction memory: A quantification of the impact on hardware complexity and WCET estimates
S Metzlaff, T Ungerer
2012 24th Euromicro Conference on Real-Time Systems, 112-121, 2012
52012
Leveraging transactional memory for a predictable execution of applications composed of hard real-time and best-effort tasks
S Metzlaff, S Weis, T Ungerer
Proceedings of the 21st International conference on Real-Time Networks and …, 2013
42013
RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor
J Wolf, M Gerdes, F Kluge, S Uhrig, J Mische, S Metzlaff, C Rochange, ...
International Journal of Computer Systems Science & Engineering 26 (6), 481-490, 2011
32011
Integration of Hard Real-Time and Organic Computing
F Kluge, J Mische, S Metzlaff, S Uhrig, T Ungerer
ACACES, 2007
32007
Analysable Instruction Memories for Hard Real-Time Systems
S Metzlaff
22012
Towards Transactional Memory for Safety-Critical Embedded Systems
S Metzlaff, S Weis, T Ungerer
12013
ISPTAP-Instruction Scratchpad Timing Analysis Program: Features and Usage
S Metzlaff
12013
Enhancing Real-Time Behaviour of Parallel Applications using Intel TSX
F Haas, S Metzlaff, S Weis, T Ungerer
2014
Otto-von-Guericke-Universitat Magdeburg
S Metzlaff, DIS Zug
2006
Gateway zwischen zeit-und ereignisgesteuerten Kommunikationsmodellen
S Metzlaff, DIS Zug
2006
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Artículos 1–20