| Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes D Nagy, G Espineira, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane IEEE Access 8, 53196-53202, 2020 | 72 | 2020 |
| Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET G Espineira, D Nagy, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane IEEE Electron Device Letters 40 (4), 510-513, 2019 | 35 | 2019 |
| A multi-method simulation toolbox to study performance and variability of nanowire FETs N Seoane, D Nagy, G Indalecio, G Espiñeira, K Kalna, A García-Loureiro Materials 12 (15), 2391, 2019 | 21 | 2019 |
| Impact of threshold voltage extraction methods on semiconductor device variability G Espiñera, D Nagy, A García-Loureiro, N Seoane, G Indalecio Solid-State Electronics 159, 165-170, 2019 | 12 | 2019 |
| Drift-Diffusion Versus Monte Carlo Simulated On-Current Variability in Nanowire FETs D NAGY, G INDALECIO, AJ GARCÍA-LOUREIRO, G ESPIÑEIRA, ... | 8* | |
| Does the threshold voltage extraction method affect device variability? G Espiñeira, AJ García-Loureiro, N Seoane IEEE Journal of the Electron Devices Society 9, 469-475, 2020 | 3 | 2020 |
| FoMPy: A figure of merit extraction tool for semiconductor device simulations G Espiñeira, N Seoane, D Nagy, G Indalecio, AJ García-Loureiro 2018 Joint International EUROSOI Workshop and International Conference on …, 2018 | 3 | 2018 |
| Parallel approach of Schrödinger-based quantum corrections for ultrascaled semiconductor devices G Espiñeira, AJ García-Loureiro, N Seoane Journal of Computational Electronics 21 (1), 10-20, 2022 | 1 | 2022 |
| Benchmarking of FinFET, Nanosheet and Nanowire FET Architectures for Future Technology Nodes AJ GARCÍA-LOUREIRO, G INDALECIO, D NAGY, N SEOANE, K KALNA, ... | | 2022 |
Antonio Garcia-LoureiroDepartment of Electronics and Computer Science. Universidad de Santiago de CompostelaVerified email at usc.es
