Soner Yaldiz
Soner Yaldiz
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TítuloCitado porAño
Formal verification of phase-locked loops using reachability analysis and continuization
M Althoff, S Yaldiz, A Rajhans, X Li, BH Krogh, L Pileggi
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 659-666, 2011
812011
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, JO Plouchart, AV Rylyakov, ...
IEEE journal of solid-state circuits 48 (5), 1138-1150, 2013
762013
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, JO Plouchart, AV Rylyakov, ...
IEEE journal of solid-state circuits 48 (5), 1138-1150, 2013
762013
The magazine archive includes every article published in Communications of the ACM for over the past 50 years.
PJ Denning
Communications of the ACM 60 (12), 20-23, 2017
74*2017
Evaluating a startup venture
MA Cusumano
Communications of the ACM 56 (10), 26-29, 2013
54*2013
SRAM parametric failure analysis
J Wang, S Yaldiz, X Li, LT Pileggi
Proceedings of the 46th Annual Design Automation Conference, 496-501, 2009
432009
An integral path self-calibration scheme for a dual-loop PLL
M Ferriss, JO Plouchart, A Natarajan, A Rylyakov, B Parker, JA Tierno, ...
IEEE journal of solid-state circuits 48 (4), 996-1008, 2013
312013
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
S Sun, F Wang, S Yaldiz, X Li, L Pileggi, A Natarajan, M Ferriss, ...
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013
222013
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
JO Plouchart, MA Ferriss, AS Natarajan, A Valdes-Garcia, B Sadhu, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (8), 2009-2017, 2013
212013
Indirect performance sensing for on-chip self-healing of analog and RF circuits
S Sun, F Wang, S Yaldiz, X Li, L Pileggi, A Natarajan, M Ferriss, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2243-2252, 2014
192014
A 21.8–27.5 GHz PLL in 32nm SOI using Gm linearization to achieve− 130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
B Sadhu, MA Ferriss, JO Plouchart, AS Natarajan, AV Rylyakov, ...
2012 IEEE Radio Frequency Integrated Circuits Symposium, 75-78, 2012
152012
Stochastic modeling and optimization for energy management in multicore systems: A video decoding case study
S Yaldiz, A Demir, S Tasiran
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
142008
Indirect phase noise sensing for self-healing voltage controlled oscillators
S Yaldiz, V Calayir, X Li, L Pileggi, AS Natarajan, MA Ferriss, J Tierno
2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011
132011
Efficient statistical analysis of read timing failures in SRAM circuits
S Yaldiz, U Arslan, X Li, L Pileggi
2009 10th International Symposium on Quality Electronic Design, 617-621, 2009
112009
Characterizing and exploiting task load variability and correlation for energy management in multi core systems
S Yaldiz, A Demir, S Tasiran, P Ienne, Y Leblebici
3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 135-140, 2005
112005
An integral path self-calibration scheme for a 20.1–26.7 GHz dual-loop PLL in 32nm SOI CMOS
M Ferriss, JO Plouchart, A Natarajan, A Rylyakov, B Parker, A Babakhani, ...
2012 Symposium on VLSI Circuits (VLSIC), 176-177, 2012
102012
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology
A Lotfy, SFS Farooq, QS Wang, S Yaldiz, P Mosalikanti, N Kurd
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015
72015
PLL bandwidth correction with offset compensation
MA Ferriss, A Natarajan, B Parker, A Rylyakov, JA Tierno, S Yaldiz
US Patent 8,493,113, 2013
72013
PLL bandwidth correction with offset compensation
MA Ferriss, A Natarajan, B Parker, A Rylyakov, JA Tierno, S Yaldiz
US Patent 8,629,701, 2014
12014
Loop parameter sensor using repetitive phase errors
M Ferriss, AS Natarajan, BD Parker, AV Rylyakov, JA Tierno, S Yaldiz
US Patent 9,157,950, 2015
2015
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