| Selective provision of error correction for memory JC Casado, X Vera, D Sanchez, T Ramirez, EH Abellanas, N Axelos US Patent 9,071,281, 2015 | 18 | 2015 |
| Evaluating dynamic core coupling in a scalable tiled-cmp architecture D Sánchez, JL Aragón, JM García International Workshop on Duplicating, Deconstructing, and Debunking (WDDD), 2008 | 14 | 2008 |
| Modeling the impact of permanent faults in caches D Sánchez, Y Sazeides, JM Cebrián, JM García, JL Aragón ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 29, 2013 | 13 | 2013 |
| An analytical model for the calculation of the expected miss ratio in faulty caches D Sánchez, Y Sazeides, JL Aragón, JM García On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International, 252-257, 2011 | 11 | 2011 |
| A log-based redundant architecture for reliable parallel computation D Sánchez, JL Aragón, JM Garcia High Performance Computing (HiPC), 2010 International Conference on, 1-10, 2010 | 11 | 2010 |
| Vulnerability estimation for cache memory JC Casado, X Vera, T Ramirez, D Sanchez, EH Abellanas, N Axelos US Patent 9,075,904, 2015 | 10 | 2015 |
| Extending SRT for parallel applications in tiled-CMP architectures D Sanchez, JL Aragon, JM Garcia Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International …, 2009 | 10 | 2009 |
| Repas: reliable execution for parallel applications in tiled-cmps D Sánchez, JL Aragón, JM García European Conference on Parallel Processing, 321-333, 2009 | 9 | 2009 |
| Increased error correction for cache memories through adaptive replacement policies X Vera, JC Casado, EH Abellanas, D Sanchez, N Axelos, T Ramirez US Patent 9,176,895, 2015 | 6 | 2015 |
| Managing power constraints in a single-core scenario through power tokens JM Cebrián, D Sánchez, JL Aragón, S Kaxiras The Journal of Supercomputing 68 (1), 414-442, 2014 | 5 | 2014 |
| Mitigating lower layer failures with adaptive system reconfiguration T Ramírez, E Herrero, N Axelos, J Carretero, N Foutris, D Sanchez, ... Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings …, 2012 | 4 | 2012 |
| Efficient inter-core power and thermal balancing for multicore processors JM Cebrián, D Sánchez, JL Aragón, S Kaxiras Computing 95 (7), 537-566, 2013 | 3 | 2013 |
| A fault-tolerant architecture for parallel applications in tiled-CMPs D Sánchez, JL Aragón, JM García The Journal of Supercomputing 61 (3), 997-1023, 2012 | 3 | 2012 |
| Banking of reliability metrics EH Abellanas, X Vera, JC Casado, T Ramirez, N Axelos, D Sanchez US Patent 9,043,659, 2015 | 2 | 2015 |
| Failure rate based control of processors EH Abellanas, X Vera, N Axelos, JC Casado, T Ramirez, DS Pedreño US Patent App. 13/730,822, 2012 | 2* | 2012 |
| Adapting dynamic core coupling to a direct-network environment D Sánchez, JL Aragón, JM García Proc. of the XIX Jornadas de Paralelismo, 2008 | 2 | 2008 |
| MEMoRy ConTRoLLER–LEVEL ExTEnSIonS foR GDDR5 SInGLE DEVICE DaTa CoRRECT SuPPoRT J Carretero, I Hernández, X Vera, T Juan, E Herrero, T Ramírez, ... Publisher Managing Editor Content Architect 17 (1), 102, 2013 | | 2013 |
| Microarchitectural Approaches for Hardware Fault Mitigation in Multicore Processors D Sánchez UNIVERSIDAD DE MURCIA, 2011 | | 2011 |
| Diseño de arquitecturas para la mitigación de fallos hardware en procesadores multinúcleo= Microarchitectural approaches for hardware fault mitigation in multicore processors D Sánchez Pedreño Murcia: Universidad de Murcia, Departamento de Ingeniería y Tecnología de …, 2011 | | 2011 |
| Modelling Permanent Fault Impact on Cache Performance D Sánchez, Y Sazeides, JL Aragón, JM Garcıa | | |
