Ajay Joshi
Ajay Joshi
Associate Professor, ECE Department, Boston University
Verified email at bu.edu - Homepage
TitleCited byYear
Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics
C Batten, A Joshi, J Orcutt, A Khilo, B Moss, CW Holzwarth, MA Popovic, ...
IEEE Micro 29 (4), 8-21, 2009
4972009
Silicon-photonic clos networks for global on-chip communication
A Joshi, C Batten, YJ Kwon, S Beamer, I Shamim, K Asanovic, ...
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 124-133, 2009
3592009
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
S Beamer, C Sun, YJ Kwon, A Joshi, C Batten, V Stojanović, K Asanović
ACM SIGARCH Computer Architecture News 38 (3), 129-140, 2010
1302010
Designing chip-level nanophotonic interconnection networks
C Batten, A Joshi, V Stojanovć, K Asanović
Integrated Optical Interconnect Architectures for Embedded Systems, 81-135, 2013
912013
Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM
M Zangeneh, A Joshi
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22 (8 …, 2014
802014
Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture
C Chen, A Joshi
Selected Topics in Quantum Electronics, IEEE Journal of 19 (2), 2013
482013
Thermal management of manycore systems with silicon-photonic networks
T Zhang, JL Abellán, A Joshi, AK Coskun
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 …, 2014
472014
Sharing and placement of on-chip laser sources in silicon-photonic NoCs
C Chen, T Zhang, P Contu, J Klamkin, AK Coskun, A Joshi
2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 88-95, 2014
412014
Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs
C Chen, T Zhang, P Contu, J Klamkin, AK Coskun, A Joshi
International Symposium on Networks-on-Chip (NOCS), 2014
412014
Asymmetric NoC Architectures for GPU Systems
AKK Ziabari, JL Abellán, Y Ma, A Joshi, D Kaeli
Network-on-chip Symposium (NOCS), 2015
322015
Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes
Z Wang, M Karpovsky, A Joshi
2010 IEEE/IFIP International Conference on Dependable Systems & Networks …, 2010
312010
Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
AJ Joshi, GG Lopez, JA Davis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (9), 990 …, 2007
292007
Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI)
A Joshi
Georgia Institute of Technology, 2006
242006
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
AJ Joshi, JA Davis
IEEE transactions on very large scale integration (VLSI) systems 13 (8), 899-910, 2005
242005
Designing energy-efficient low-diameter on-chip networks with equalized interconnects
A Joshi, B Kim, V Stojanovic
2009 17th IEEE Symposium on High Performance Interconnects, 3-12, 2009
232009
Run-time energy management of manycore systems through reconfigurable interconnects
J Meng, C Chen, AK Coskun, A Joshi
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
222011
UMH: A hardware-based unified memory hierarchy for systems with multiple discrete GPUs
AK Ziabari, Y Sun, Y Ma, D Schaa, JL Abellán, R Ubal, J Kim, A Joshi, ...
ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-25, 2016
212016
Detecting hardware trojans using backside optical imaging of embedded watermarks
B Zhou, R Adato, M Zangeneh, T Yang, A Uyar, B Goldberg, S Unlu, ...
Proceedings of the 52nd Annual Design Automation Conference (DAC), 111, 2015
212015
Towards General-Purpose Neural Network Computing
S Eldridge, A Waterland, M Seltzer, J Appavoo, A Joshi
Parallel Architectures and Compilation Techniques (PACT), 2015
202015
Performance and energy models for memristor-based 1T1R RRAM cell
M Zangeneh, A Joshi
Proceedings of the great lakes symposium on VLSI, 9-14, 2012
202012
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