Carlos Villavieja
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Didi: Mitigating the performance impact of tlb shootdowns using a shared tlb directory
C Villavieja, V Karakostas, L Vilanova, Y Etsion, A Ramirez, A Mendelson, ...
2011 International Conference on Parallel Architectures and Compilation …, 2011
1182011
The low power architecture approach towards exascale computing
N Rajovic, L Vilanova, C Villavieja, N Puzovic, A Ramirez
Journal of Computational Science 4 (6), 439-443, 2013
1032013
Sinuca: A validated micro-architecture simulator
MAZ Alves, C Villavieja, M Diener, FB Moreira, POA Navaux
2015 IEEE 17th International Conference on High Performance Computing and …, 2015
352015
Scalable simulation of decoupled accelerator architectures
A Rico, F Cabarcas, A Quesada, M Pavlovic, AJ Vega, C Villavieja, ...
Universitat Politecnica de Catalunya, Tech. Rep. UPCDAC-RR-2010-14, 2010
262010
On the simulation of large-scale architectures using multiple application abstraction levels
A Rico, F Cabarcas, C Villavieja, M Pavlovic, A Vega, Y Etsion, A Ramirez, ...
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012
242012
Energy savings via dead sub-block prediction
MAZ Alves, E Ebrahimi, VT Narasiman, C Villavieja, POA Navaux, YN Patt
2012 IEEE 24th International Symposium on Computer Architecture and High …, 2012
192012
Yoga: A hybrid dynamic VLIW/OoO processor
C Villavieja, JA Joao, R Miftakhutdinov, YN Patt
no. HPS Technical Report, 2014
122014
FELI: HW/SW support for on-chip distributed shared memory in multicores
C Villavieja, Y Etsion, A Ramirez, N Navarro
European Conference on Parallel Processing, 282-294, 2011
102011
Adaptive runtime-assisted block prefetching on chip-multiprocessors
V Garcia, A Rico, C Villavieja, P Carpenter, N Navarro, A Ramirez
International journal of parallel programming 45 (3), 530-550, 2017
62017
Memory management on chip-multiprocessors with on-chip memories
C Villavieja, I Gelado, A Ramirez, N Navarro
Proc. Workshop on the Interaction between Operating Systems and Computer …, 2008
62008
Energy efficient last level caches via last read/write prediction
MAZ Alves, C Villavieja, M Diener, POA Navaux
2013 25th International Symposium on Computer Architecture and High …, 2013
52013
Yoga: A hybrid dynamic VLIW
C Villavieja, JA Joao, R Miftakhutdinov, YN Patt
OoO processor, 2014
42014
Cómo evaluar continua e individualmente en asignaturas basadas en proyectos
L Velasco, C Villavieja
Actas de las XV Jornadas de Enseñanza Universitaria de Informática, JENUI …, 2009
42009
Physics-based time-domain model of a magnetic induction microgenerator
L Mateu, C Villavieja, F Moll
IEEE transactions on magnetics 43 (3), 992-1001, 2007
42007
The Data Transfer Engine: Towards a Software Controlled Memory Hierarchy
V Garcia, A Rico, C Villavieja, N Navarro, A Ramirez
Advanced Computer Architecture and Compilation for Embedded Systems, 215-218, 2012
22012
Hardware Support for Explicit Communication in Scalable CMP’s
C Villavieja, M Katevenis, N Navarro, D Pnevmatikatos, A Ramirez, ...
Computer Architecture Dept., Polythecnic University of Catalonia (UPC …, 2008
22008
On-chip distributed shared memory
C Villavieja, A Ramirez, N Navarro
Tech. Rep. UPC-DAC-RR-CAP-2011, Universitat Politecnica de Catalunya …, 0
1
On the Simulation of Large-scale Architecture Using Multiple Application Abstraction Levels
MV Alejandro Rico, Felipe Cabarcas, Carlos Villavieja
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Paper …, 2012
2012
Article 36 (20 pages)-On the Simulation of Large-Scale Architectures Using Multiple Application Abstraction Levels
A Rico, F Cabarcas, C Villavieja, M Pavlovic, A Vega, Y Etsion, A Ramirez, ...
ACM Transactions on Architecture and Code Optimization-TACO 8 (4), 2011
2011
PACT 2019
A Zaks, B Motik, C Villavieja, F Aurangzeb, G Blelloch, J Huang, J Shun, ...
En aquests moments el sistema no pot dur a terme l'operació. Torneu-ho a provar més tard.
Articles 1–20