Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors R Jevtic, HP Le, M Blagojevic, S Bailey, K Asanovic, E Alon, B Nikolic IEEE, 2014 | 58 | 2014 |

An agile approach to building risc-v microprocessors Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ... IEEE Micro 36 (2), 8-20, 2016 | 53 | 2016 |

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ... IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016 | 48 | 2016 |

Power measurement methodology for FPGA devices R Jevtic, C Carreras Instrumentation and Measurement, IEEE Transactions on 60 (1), 237-247, 2011 | 38 | 2011 |

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ... VLSI Circuits (VLSI Circuits), 2015 Symposium on, C316-C317, 2015 | 33 | 2015 |

Power estimation of embedded multiplier blocks in FPGAs R Jevtic, C Carreras Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 18 (5 …, 2010 | 30 | 2010 |

Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits J Jeon, L Hutin, R Jevtic, N Liu, Y Chen, R Nathanael, W Kwon, ... Electron Device Letters, IEEE 33 (2), 281-283, 2012 | 23 | 2012 |

A complete dynamic power estimation model for data-paths in FPGA DSP designs R Jevtic, C Carreras Integration, the VLSI Journal 45 (2), 172-185, 2012 | 19 | 2012 |

Technology variability from a design perspective B Nikolic, JH Park, J Kwak, B Giraud, Z Guo, LT Pang, SO Toh, R Jevtic, ... Circuits and Systems I: Regular Papers, IEEE Transactions on 58 (9), 1996-2009, 2011 | 19 | 2011 |

Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models R Jevtic, C Carreras, G Caffarena International Journal of Electronics 95 (7), 653-668, 2008 | 17 | 2008 |

Fully integrated DC-DC converter and a 0.4 V 32-bit CPU with timing-error prevention supplied from a prototype 1.55 V Li-ion battery M Turnquist, M Hiienkari, J Makipaa, R Jevtic, E Pohjalainen, T Kallio, ... VLSI Circuits (VLSI Circuits), 2015 Symposium on, C320-C321, 2015 | 16 | 2015 |

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015 | 15 | 2015 |

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits B Jovanovic, R Jevtic, C Carreras Industrial Informatics, IEEE Transactions on 10 (1), 393-398, 2014 | 15 | 2014 |

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes P Barrio, C Carreras, JA López, Ó Robles, R Jevtic, R Sierra Journal of Systems Architecture 60 (7), 579-591, 2014 | 7 | 2014 |

Power estimation of dividers implemented in FPGAs R Jevtic, B Jovanovic, C Carreras Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 7 | 2011 |

Analytical High-level Power model for LUT-based Components C Carreras Vaquer, R Jevtic Springer Verlag, 2009 | 6* | 2009 |

Analytical high-level power model for LUT-based components R Jevtic, C Carreras Integrated Circuit and System Design. Power and Timing Modeling …, 2009 | 6 | 2009 |

Switching activity models for power estimation in FPGA multipliers R Jevtic, C Carreras, G Caffarena Reconfigurable Computing: Architectures, Tools and Applications, 201-213, 2007 | 6 | 2007 |

Floorplan-based FPGA interconnect power estimation in DSP circuits R Jevtic, C Carreras, V Pejovic Proceedings of the 11th international workshop on System level interconnect …, 2009 | 3 | 2009 |

Triple-bit method for power estimation of nonlinear digital circuits in FPGAs B Jovanovic, R Jevtic, C Carreras Electronics Letters 46 (13), 903-905, 2010 | 2 | 2010 |