Peeter Ellervee
Peeter Ellervee
Professor of Computer Engineering, Tallinn University of Technology
Verified email at ati.ttu.ee
Title
Cited by
Cited by
Year
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
A Hemani, T Meincke, S Kumar, A Postula, T Olsson, P Nilsson, J Oberg, ...
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 873-878, 1999
2081999
Hardware/software partitioning and minimizing memory interface traffic
A Jantsch, P Ellervee, A Hemani, J Öberg, H Tenhunen
European Design Automation Conference: Proceedings of the conference on …, 1994
1361994
A case study on hardware/software partitioning
A Jantsch, P Ellervee, J Oberg, A Hemani
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 111-118, 1994
961994
Globally asynchronous locally synchronous architecture for large high-performance ASICs
T Meincke, A Hemani, S Kumar, P Ellervee, J Oberg, T Olsson, P Nilsson, ...
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits …, 1999
561999
System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory
K Puttaswamy, KW Choi, JC Park, VJ Mooney III, A Chatterjee, P Ellervee
Proceedings of the 15th international symposium on System Synthesis, 225-230, 2002
332002
Ellervee” A fast algorithm for threelevel logic optimization
E Dubrova, P Ellervee
Proc. int. workshop on logic synthesis, Lake Tahoe, 1999
241999
A software oriented approach to hardware/software codesign
A Jantsch, P Ellervee, J Oberg, A Hemani, H Tenhunen
Proc. of the Poster Session of CC, 1994
221994
Method and apparatus for encoding/decoding n-bit data into 2n-bit codewords
A Djupsjöbacka, P Ellervee, M Mokhtari
US Patent 6,232,895, 2001
192001
Method and apparatus for encoding/decoding n-bit data into 2n-bit codewords
A Djupsjöbacka, P Ellervee, M Mokhtari
US Patent 6,232,895, 2001
192001
FPGA-based fault emulation of synchronous sequential circuits
P Ellervee, J Raik, K Tammemäe, RJ Ubar
IET Computers & Digital Techniques 1 (2), 70-76, 2007
182007
FPGA-based fault emulation of synchronous sequential circuits
P Ellervee, J Raik, K Tammemäe, RJ Ubar
IET Computers & Digital Techniques 1 (2), 70-76, 2007
182007
High-level synthesis of control and memory intensive applications
P Ellervee
Institutionen för elektronisk systemkonstruktion, 2000
172000
Code coverage analysis using high-level decision diagrams
J Raik, U Reinsalu, R Ubar, M Jenihhin, P Ellervee
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008
162008
Evaluating benefits of globally asynchronous locally synchronous VLSI architecture
T Meincke, A Hemani, P Ellervee, J Öberg, S Kumar, D Lindqvist, ...
NORCHIP, 50-57, 1998
151998
Exploiting data transfer locality in memory mapping
P Ellervee, M Miranda, F Catthoor, A Hemani
Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for …, 1999
141999
Open Source On-Chip Logic Analyzer for FPGA-s
L Ehrenpreis, P Ellervee, K Tammemae
2006 International Biennial Baltic Electronics Conference, 1-4, 2006
112006
Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
J Oberg, J Plosila, P Ellervee
2005 NORCHIP, 200-205, 2005
112005
System-level data-format exploration for dynamically allocated data structures
P Ellervee, M Miranda, F Catthoor, A Hemani
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
112001
Comparing conventional HLS with grammar-based hardware synthesis: a case study
J Öberg, P Ellervee, A Kumar, A Hemani
NORCHIP, 52-59, 1997
111997
High-level decision diagram manipulations for code coverage analysis
K Minakova, U Reinsalu, A Chepurov, J Raik, M Jenihhin, R Ubar, ...
2008 11th International Biennial Baltic Electronics Conference, 207-210, 2008
102008
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