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Dureseti Chidambarrao
Dureseti Chidambarrao
STSM, IBM
Verified email at us.ibm.com
Title
Cited by
Cited by
Year
Vertical fin-fet mos devices
D Chidambarrao, J Beintner, R Divakaruni
US Patent 7,683,428, 2010
2482010
High performance strained silicon FinFETs device and method for forming same
SW Bedell, KK Chan, D Chidambarrao, SH Christianson, JO Chu, ...
US Patent 7,705,345, 2010
2462010
Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model
MK Ieong, PM Solomon, SE Laux, HSP Wong, D Chidambarrao
International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998
2361998
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
HS Yang, R Malik, S Narasimha, Y Li, R Divakaruni, P Agnello, S Allen, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
2342004
Methods and system for analysis and management of parametric yield
JA Culp, P Chang, D Chidambarrao, P Elakkumanan, J Hibbeler, ...
US Patent 8,042,070, 2011
2312011
Structure and method to improve channel mobility by gate electrode stress modification
MP Belyansky, D Chidambarrao, OH Dokumaci, BB Doris, O Gluschenkov
US Patent 6,977,194, 2005
2182005
Stress inducing spacers
D Chidambarrao, OH Dokumaci, BB Doris, JA Mandelman, X Baie
US Patent 6,825,529, 2004
2082004
Strained finFETs and method of manufacture
D Chidambarrao, OH Dokumaci, OG Gluschenkov
US Patent 7,198,995, 2007
1912007
Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
H Chen, D Chidambarrao, OG Gluschenkov, AL Steegen, HS Yang
US Patent 6,891,192, 2005
1842005
High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization
CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ...
2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014
1762014
Strained finFET CMOS device structures
BB Doris, D Chidambarrao, M Ieong, JA Mandelman
US Patent 7,388,259, 2008
1702008
High performance stress-enhanced MOSFETs using Si: C and SiGe epitaxial source/drain and method of manufacture
H Chen, D Chidambarrao, OH Dokumaci
US Patent 7,303,949, 2007
1682007
SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
BB Doris, D Chidambarrao, X Baie, JA Mandelman, DK Sadana, ...
US Patent 6,717,216, 2004
1672004
Isolation structures for imposing stress patterns
D Chidambarrao, OH Dokumaci, BB Doris, JA Mandelman
US Patent 6,974,981, 2005
1542005
High performance CMOS device structures and method of manufacture
BB Doris, D Chidambarrao, SH Ku
US Patent 7,279,746, 2007
1442007
Stress inducing spacers
D Chidambarrao, OH Dokumaci, BB Doris, JA Mandelman, X Baie
US Patent 7,374,987, 2008
1422008
Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
D Chidambarrao, O Dokumaci
US Patent 7,060,539, 2006
1332006
Strain effects on device characteristics: Implementation in drift-diffusion simulators
JL Egley, D Chidambarrao
Solid-State Electronics 36 (12), 1653-1664, 1993
1311993
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Y Liu, D Chidambarrao, O Gluschenkov, JR Holt, RT Mo, K Rim
US Patent 8,217,423, 2012
1302012
Silicon device on Si: C-OI and SGOI and method of manufacture
D Chidambarrao, OH Dokumaci, OG Gluschenkov
US Patent 7,247,534, 2007
1232007
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