Seung-Jun Bae
TitleCited byYear
Memory system having multi-terminated multi-drop bus
HJ Park, SJ Bae
US Patent 7,274,583, 2007
912007
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion
SJ Bae, KI Park, JD Ihm, HY Song, WJ Lee, HJ Kim, KH Kim, YS Park, ...
IEEE journal of solid-state circuits 43 (1), 121-131, 2008
582008
A 3.2 gbps/pin 8 gbit 1.0 v lpddr4 sdram with integrated ecc engine for sub-1 v dram core operation
TY Oh, H Chung, JY Park, KW Lee, S Oh, SY Doo, HJ Kim, CY Lee, ...
IEEE Journal of Solid-State Circuits 50 (1), 178-190, 2014
532014
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation
YS Sohn, SJ Bae, HJ Park, CH Kim, SI Cho
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003 …, 2003
512003
A 60nm 6Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques
SJ Bae, YS Sohn, KI Park, KH Kim, DH Chung, JG Kim, SH Kim, MS Park, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
502008
Majority voter circuits and semiconductor device including the same
SJ Bae, JD Lim, GS Moon, KII Park
US Patent App. 12/656,590, 2010
402010
Digital duty cycle correction circuit and method for multi-phase clock
HJ Park, YC Jang, SJ Bae
US Patent 6,958,639, 2005
392005
Latency control circuit and semiconductor memory device comprising same
SH Kim, SJ Bae, HR Kim, HS Seol
US Patent App. 13/743,412, 2013
382013
A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients
SJ Bae, HJ Chi, HR Kim, HJ Park
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
382005
AC-coupling phase interpolator and delay-locked loop using the same
JG Kim, KII Park, SJ Bae, SH Kim, DH Chung
US Patent 8,004,328, 2011
352011
A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme
SJ Bae, HJ Chi, YS Sohn, HJ Park
IEEE journal of solid-state circuits 40 (5), 1119-1129, 2005
352005
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
SJ Bae, YS Sohn, TY Oh, SH Kim, YS Yang, DH Kim, SH Kwak, HS Seol, ...
2011 IEEE International Solid-State Circuits Conference, 498-500, 2011
332011
An all-digital 90-degree phase-shift DLL with loop-embedded DCC for 1.6 Gbps DDR interface
JH Bae, JH Seo, HS Yeo, JW Kim, JY Sim, HJ Park
2007 IEEE Custom Integrated Circuits Conference, 373-376, 2007
332007
Low power balance code using data bus inversion
SJ Bae
US Patent 7,495,587, 2009
282009
A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise
SJ Bae, HJ Chi, YS Sohn, HJ Park
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004
282004
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM with 2.5 ns bank to bank active time and no bank group restriction
TY Oh, YS Sohn, SJ Bae, MS Park, JH Lim, YK Cho, DH Kim, DM Kim, ...
IEEE Journal of Solid-State Circuits 46 (1), 107-118, 2010
272010
On-die termination circuit, data output buffer and semiconductor memory device
HS Seol, YS Sohn, DM Kim, JI Lee, KI Park, SJ Bae, S Kwak
US Patent 8,531,898, 2013
242013
Circuit and method for removing skew in data transmitting/receiving system
SJ Bae, KI Park, SJ Jang
US Patent 8,045,663, 2011
232011
A single-loop SS-LMS algorithm with single-ended integrating DFE receiver for multi-drop DRAM interface
HJ Chi, JS Lee, SH Jeon, SJ Bae, YS Sohn, JY Sim, HJ Park
IEEE journal of solid-state circuits 46 (9), 2053-2063, 2011
232011
A delay locked loop with a feedback edge combiner of duty-cycle corrector with a 20%–80% input duty cycle for SDRAMs
JH Lim, JH Bae, J Jang, HK Jung, H Lee, Y Kim, B Kim, JY Sim, HJ Park
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (2), 141-145, 2015
222015
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