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Mario Daniel Ruiz Noguera
Mario Daniel Ruiz Noguera
Member of Technical Staff at AMD
Dirección de correo verificada de amd.com - Página principal
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Año
Limago: An FPGA-based open-source 100 GbE TCP/IP stack
M Ruiz, D Sidler, G Sutter, G Alonso, S López-Buedo
2019 29th International Conference on Field Programmable Logic and …, 2019
712019
Elastic-df: Scaling performance of dnn inference in fpga clouds through automatic partitioning
T Alonso, L Petrica, M Ruiz, J Petri-Koenig, Y Umuroglu, I Stamelos, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15 (2), 1-34, 2021
282021
Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks
M Ruiz, J Ramos, G Sutter, JEL de Vergara, S López-Buedo, J Aracil
IEEE Communications Magazine 54 (3), 80-87, 2016
152016
A single-fpga architecture for detecting heavy hitters in 100 gbit/s ethernet links
JF Zazo, S Lopez-Buedo, M Ruiz, G Sutter
2017 International Conference on ReConFigurable Computing and FPGAs …, 2017
132017
Modeling and assessing connectivity services performance in a sandbox domain
M Ruiz, M Ruiz, F Tabatabaeimehr, L Gifre, S López-Buedo, ...
Journal of Lightwave Technology 38 (12), 3180-3189, 2020
92020
Fpga-based tcp/ip checksum offloading engine for 100 gbps networks
G Sutter, M Ruiz, S Lopez-Buedo, G Alonso
2018 International Conference on ReConFigurable Computing and FPGAs …, 2018
92018
FPGA-based encrypted network traffic identification at 100 Gbit/s
M Ruiz, G Sutter, S López-Buedo, JEL de Vergara
2016 International Conference on ReConFigurable Computing and FPGAs …, 2016
72016
Demonstration of 100 Gbit/s active measurements in dynamically provisioned optical paths
JEL de Vergara, M Ruiz, L Gifre, L Vaquero, JF Zazo, S López-Buedo, ...
IET Digital Library, 2019
52019
Submicrosecond latency video compression in a low-end FPGA-based system-on-chip
T Alonso, M Ruiz, ÁL García-Arias, G Sutter, JEL de Vergara
2018 28th International Conference on Field Programmable Logic and …, 2018
52018
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices
M Ruiz, J Ramos, G Sutter, S López-Buedo, JEL de Vergara, C Sisterna
2016 26th International Conference on Field Programmable Logic and …, 2016
32016
Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes
M Ruiz, G Sutter, S López-Buedo, J Ramos, JEL de Vergara, J Aracil
2015 International Conference on ReConFigurable Computing and FPGAs …, 2015
32015
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks
M Ruiz, G Sutter, S López-Buedo, JF Zazo, JEL de Vergara
2017 International Conference on ReConFigurable Computing and FPGAs …, 2017
22017
Towards 100 GbE FPGA-Based Flow Monitoring
T Alonso, M Ruiz, G Sutter, S López-Buedo, JEL De Vergara
2019 X Southern Conference on Programmable Logic (SPL), 9-16, 2019
12019
Monitorización con FPGAs de flujos y sesiones TCP en enlaces de 40 Gbit/s
T Alonso, M Ruiz, G Sutter, C Sisterna, S López-Buedo, JEL de Vergara
Jornadas Sarteco, 2018
12018
Tutorial: Introduction to the AMD Versal ACAP Adaptable Intelligent Engine and to its Programming Model
MD Ruiz Noguera, C McCabe
Proceedings of the 2023 International Conference on Hardware/Software …, 2023
2023
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Artículos 1–15