| Design issues and implementations for floating-point divide–add fused A Amaricai, M Vladutiu, O Boncalo IEEE Transactions on Circuits and Systems II: Express Briefs 57 (4), 295-299, 2010 | 54 | 2010 |
| An FPGA sliding window-based architecture Harris corner detector A Amaricai, CE Gavriliu, O Boncalo 2014 24th International Conference on Field Programmable Logic and …, 2014 | 42 | 2014 |
| FPGA design of high throughput LDPC decoder based on imprecise offset min-sum decoding T Nguyen-Ly, K Le, F Ghaffari, A Amaricai, O Boncalo, V Savin, ... 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015 | 37 | 2015 |
| Layered LDPC decoders with efficient memory access scheduling and mapping and built-in support for pipeline hazards mitigation O Boncalo, G Kolumban-Antal, A Amaricai, V Savin, D Declercq IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1643-1656, 2018 | 23 | 2018 |
| Linear compositional delay model for the timing analysis of sub-powered combinational circuits J Chen, C Spagnol, S Grandhi, E Popovici, S Cotofana, A Amaricai 2014 IEEE Computer Society Annual Symposium on VLSI, 380-385, 2014 | 21 | 2014 |
| FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization S Nimara, O Boncalo, A Amaricai, M Popa 2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016 | 17 | 2016 |
| Probabilistic gate level fault modeling for near and sub-threshold CMOS circuits A Amaricai, S Nimara, O Boncalo, J Chen, E Popovici 2014 17th Euromicro Conference on Digital System Design, 473-479, 2014 | 17 | 2014 |
| Ultra high throughput unrolled layered architecture for QC-LDPC decoders O Boncalo, A Amaricai 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 225-230, 2017 | 16 | 2017 |
| Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing O Boncalo, A Amaricai, A Hera, V Savin 2014 24th International Conference on Field Programmable Logic and …, 2014 | 16 | 2014 |
| Memory efficient FPGA implementation for flooded LDPC decoder A Amaricai, O Boncalo, I Mot 2015 23rd telecommunications forum Telfor (TELFOR), 500-503, 2015 | 15 | 2015 |
| Design trade-offs in configurable FPGA architectures for k-means clustering A Amaricai Studies in Informatics and Control 26 (1), 43-48, 2017 | 13 | 2017 |
| Memory trade-offs in layered self-corrected min-sum LDPC decoders O Boncalo, A Amaricai, PF Mihancea, V Savin Analog Integrated Circuits and Signal Processing 87, 169-180, 2016 | 10 | 2016 |
| Low‐precision DSP‐based floating‐point multiply‐add fused for Field Programmable Gate Arrays A Amaricai, O Boncalo, CE Gavriliu IET Computers & Digital Techniques 8 (4), 187-197, 2014 | 10 | 2014 |
| Design of addition and multiplication units for high performance interval arithmetic processor A Amaricai, M Vladutiu, L Prodan, M Udrescu, O Boncalo 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-4, 2007 | 10 | 2007 |
| Using simulated fault injection for fault tolerance assessment of quantum circuits O Boncalo, M Udrescu, L Prodan, M Vladutiu, A Amaricai 40th Annual Simulation Symposium (ANSS'07), 213-220, 2007 | 10 | 2007 |
| Configurable fpga architecture for hardware-software merge sorting PC Petrut, A Amaricai, O Boncalo 2016 MIXDES-23rd International Conference Mixed Design of Integrated …, 2016 | 9 | 2016 |
| Cost effective FPGA probabilistic fault emulation O Boncalo, A Amaricai, C Spagnol, E Popovici 2014 NORCHIP, 1-4, 2014 | 9 | 2014 |
| Design of floating point units for interval arithmetic A Amaricai, M Vladutiu, O Boncalo 2009 Ph. D. Research in Microelectronics and Electronics, 12-15, 2009 | 8 | 2009 |
| Timing error analysis of flooded LDPC decoders A Amaricai, V Savin, O Boncalo, N Cucu-Laurenciu, J Chen, S Cotofana 2015 IEEE International Conference on Microwaves, Communications, Antennas …, 2015 | 7 | 2015 |
| Check node unit for LDPC decoders based on one‐hot data representation of messages O Boncalo, A Amaricai, V Savin, D Declercq, F Ghaffari Electronics Letters 51 (12), 907-908, 2015 | 7 | 2015 |
