| 8 Gb 3-D DDR3 DRAM using through-silicon-via technology U Kang, HJ Chung, S Heo, DH Park, H Lee, JH Kim, SH Ahn, SH Cha, ... IEEE Journal of Solid-State Circuits 45 (1), 111-119, 2009 | 680 | 2009 |
| A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth Y Choi, I Song, MH Park, H Chung, S Chang, B Cho, J Kim, Y Oh, D Kwon, ... 2012 IEEE International Solid-State Circuits Conference, 46-48, 2012 | 452 | 2012 |
| Stacked memory device K Uk-Song, JB Lee, H Chung US Patent 7,999,367, 2011 | 150 | 2011 |
| Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory H Chung, JB Lee, K Uk-Song US Patent 7,830,692, 2010 | 132 | 2010 |
| A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM with integrated ECC engine for sub-1 V DRAM core operation TY Oh, H Chung, JY Park, KW Lee, S Oh, SY Doo, HJ Kim, CY Lee, ... IEEE Journal of Solid-State Circuits 50 (1), 178-190, 2014 | 113 | 2014 |
| Stacked memory module and system K Uk-Song, H Chung, JS Choi, H Lee US Patent 8,031,505, 2011 | 113 | 2011 |
| A 58nm 1.8 v 1gb pram with 6.4 mb/s program bw H Chung, BH Jeong, BJ Min, Y Choi, BH Cho, J Shin, J Kim, J Sunwoo, ... 2011 IEEE International Solid-State Circuits Conference, 500-502, 2011 | 109 | 2011 |
| Process variation compensated multi-chip memory package H Chung US Patent 8,054,663, 2011 | 107 | 2011 |
| Multi-chip memory devices and methods of controlling the same H Chung US Patent 8,996,759, 2015 | 88 | 2015 |
| A 512-mb DDR3 SDRAM prototype with C/sub IO/minimization and self-calibration techniques C Park, HJ Chung, YS Lee, J Kim, JJ Lee, MS Chae, DH Jung, SH Choi, ... IEEE journal of solid-state circuits 41 (4), 831-838, 2006 | 58 | 2006 |
| Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin/spl times/16 DDR SDRAM JB Lee, KH Kim, C Yoo, S Lee, OG Na, CY Lee, HY Song, JS Lee, ZH Lee, ... 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001 | 44 | 2001 |
| Semiconductor memory devices and memory systems including the same YI Kim, H Chung US Patent 9,767,920, 2017 | 31 | 2017 |
| Semiconductor memory device and memory system including the same H Chung, K Kim US Patent 7,882,417, 2011 | 31 | 2011 |
| Memory system mounted directly on board and associated method JB Lee, H Chung US Patent 7,227,796, 2007 | 23 | 2007 |
| Methods of operating non-volatile memory devices during write operation interruption, non-volatile memory devices, memories and electronic systems operating the same KJ Lee, YT Lee, WY Cho, HJ Chung US Patent 8,713,408, 2014 | 22 | 2014 |
| Memory system having low power consumption H Chung, JB Lee, JS Choi US Patent 7,930,492, 2011 | 18 | 2011 |
| Output driver H Chung, YC Jang US Patent 7,463,073, 2008 | 18 | 2008 |
| Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory H Chung, JB Lee, K Uk-Song US Patent App. 12/938,570, 2011 | 17 | 2011 |
| Apparatuses and method for multi-level communication YC Jang, H Chung US Patent App. 12/230,578, 2009 | 17 | 2009 |
| Stacked memory module and system K Uk-Song, H Chung, JS Choi, H Lee US Patent 8,369,123, 2013 | 16 | 2013 |
Hoon LeeAssistant Professor, Kyung Hee University, Seoul, South KoreaVerified email at khu.ac.kr
