Electroencephalography based fusion two-dimensional (2D)-convolution neural networks (CNN) model for emotion recognition system YH Kwon, SB Shin, SD Kim Sensors 18 (5), 1383, 2018 | 175 | 2018 |
Design and evaluation of a selective compressed memory system JS Lee, WK Hong, SD Kim Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999 | 135 | 1999 |
Task scheduling in distributed computing systems with a genetic algorithm SH Woo, SB Yang, SD Kim, TD Han Proceedings High Performance Computing on the Information Superhighway. HPC …, 1997 | 75 | 1997 |
Augmenting the optimal selection theory for superconcurrency MC Wang, SD Kim, MA Nichols, RF Freund, HJ Siegel, WG Nation Proc. Workshop on Heterogeneous Processing, 13-21, 1992 | 74 | 1992 |
Personalized service discovery in ubiquitous computing environments KL Park, UH Yoon, SD Kim IEEE Pervasive Computing 8 (1), 58-65, 2008 | 59 | 2008 |
An on-chip cache compression technique to reduce decompression overhead and design complexity JS Lee, WK Hong, SD Kim Journal of systems Architecture 46 (15), 1365-1382, 2000 | 57 | 2000 |
An Efficient Stochastic Anti-Collision Algorithm Using Bit-Slot Mechanism. CS Kim, KL Park, H Kim, SD Kim PDPTA, 652-656, 2004 | 56 | 2004 |
Real-time visual–inertial SLAM based on adaptive keyframe selection for mobile AR applications JC Piao, SD Kim IEEE Transactions on Multimedia 21 (11), 2827-2836, 2019 | 51 | 2019 |
Adaptive monocular visual–inertial SLAM for real-time augmented reality applications in mobile devices JC Piao, SD Kim Sensors 17 (11), 2567, 2017 | 45 | 2017 |
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities JH Lee, GH Park, SD Kim Journal of Systems Architecture 51 (2), 111-123, 2005 | 44 | 2005 |
A low power TLB structure for embedded systems JH Choi, JH Lee, SW Jeong, SD Kim, C Weems IEEE Computer Architecture Letters 1 (1), 3-3, 2002 | 44 | 2002 |
A selective filter-bank TLB system JH Lee, GH Park, SB Park, SD Kim Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 42 | 2003 |
A pattern adaptive NAND flash memory storage structure SH Park, JW Park, SD Kim, CC Weems IEEE transactions on computers 61 (1), 134-138, 2010 | 40 | 2010 |
Modeling overlapped operation between the control unit and processing elements in an SIMD machine SD Kim, MA Nichols, HJ Siegel journal of parallel and distributed computing 12 (4), 329-342, 1991 | 40 | 1991 |
A new cache architecture based on temporal and spatial locality JH Lee, JS Lee, SD Kim Journal of Systems Architecture 46 (15), 1451-1467, 2000 | 39 | 2000 |
Limitations imposed on mixed-mode performance of optimized phases due to temporal juxtaposition TB Berg, SD Kim, HJ Siegel Journal of Parallel and Distributed Computing 13 (2), 154-169, 1991 | 38 | 1991 |
A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk JW Park, SH Park, CC Weems, SD Kim Microprocessors and Microsystems 35 (1), 48-59, 2011 | 35 | 2011 |
An intelligent cache system with hardware prefetching for high performance JH Lee, S Jeong, SD Kim, CC Weems IEEE Transactions on Computers 52 (5), 607-616, 2003 | 35 | 2003 |
Cache memory system and method for managing the same TD Han, GH Park, SD Kim US Patent 6,549,983, 2003 | 34 | 2003 |
A mixed flash translation layer structure for SLC-MLC combined flash memory system SH Park, J Park, J Jeong, J Kim, S Kim Proceedings of the 1th International Workshop on Storage and I/O …, 2008 | 33 | 2008 |