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Felipe S Marranghello
Felipe S Marranghello
Verified email at inf.ufrgs.br
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Cited by
Year
Factored forms for memristive material implication stateful logic
FS Marranghello, V Callegaro, MGA Martins, AI Reis, RP Ribas
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015
262015
maj- Logic Synthesis for Emerging Technology
A Neutzling, FS Marranghello, JM Matos, A Reis, RP Ribas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
152019
SOP based logic synthesis for memristive IMPLY stateful logic
FS Marranghello, V Callegaro, AI Reis, RP Ribas
2015 33rd IEEE International Conference on Computer Design (ICCD), 228-235, 2015
152015
Four-level forms for memristive material implication logic
FS Marranghello, V Callegaro, AI Reis, RP Ribas
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5 …, 2019
122019
Improved logic synthesis for memristive stateful logic using multi-memristor implication
FS Marranghello, V Callegaro, MGA Martins, AI Reis, RP Ribas
2015 IEEE international symposium on circuits and systems (ISCAS), 181-184, 2015
122015
Majority-based logic synthesis for nanometric technologies
MGA Martins, V Callegaro, FS Marranghello, RP Ribas, AI Reis
14th IEEE International Conference on Nanotechnology, 256-261, 2014
122014
Spin diode network synthesis using functional composition
MGA Martins, FS Marranghello, JS Friedman, AV Sahakian, RP Ribas, ...
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
112013
Impact and optimization of lithography-aware regular layout in digital circuit design
V Dal Bem, P Butzen, FS Marranghello, AI Reis, RP Ribas
2011 IEEE 29th International Conference on Computer Design (ICCD), 279-284, 2011
112011
SAT-sweeping enhanced for logic synthesis
L Amarú, F Marranghello, E Testa, C Casares, V Possani, J Luo, P Vuillod, ...
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
92020
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis
V Callegaro, FS Marranghello, MGA Martins, RP Ribas, AI Reis
2015 33rd IEEE International Conference on Computer Design (ICCD), 680-687, 2015
92015
CMOS inverter analytical delay model considering all operating regions
FS Marranghello, AI Reis, RP Ribas
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1452-1455, 2014
92014
CMOS inverter delay model based on DC transfer curve for slow input
FS Marranghello, AI Reis, RP Ribas
International Symposium on Quality Electronic Design (ISQED), 651-657, 2013
82013
LUT-based optimization for ASIC design flow
L Amarú, V Possani, E Testa, F Marranghello, C Casares, J Luo, P Vuillod, ...
2021 58th ACM/IEEE Design Automation Conference (DAC), 871-876, 2021
72021
One-sided countermeasures for side-channel attacks can backfire
Y Yu, F Marranghello, VD Teijeira, E Dubrova
Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and …, 2018
72018
Exact benchmark circuits for logic synthesis
WL Neto, VN Possani, FS Marranghello, JM Matos, PE Gaillardon, AI Reis, ...
IEEE Design & Test 37 (3), 51-58, 2019
52019
Improving analytical delay modeling for CMOS inverters
FS Marranghello, RP Ribas, AI Reis
Journal of integrated circuits and systems. Porto Alegre. Vol. 10, no. 2 …, 2015
52015
Enhanced spin-diode synthesis using logic sharing
M Martins, F Marranghello, J Friedman, A Sahakian, R Ribas, A Reis
2015 Euromicro Conference on Digital System Design, 218-224, 2015
32015
Delay model for static CMOS complex gates
FS Marranghello, AI Reis, RP Ribas
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
32013
Design-oriented delay model for CMOS inverter
FS Marranghello, AI Reis, RP Ribas
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012
32012
Evaluation of Diferrent XOR Gates
AW Júnior, FS Marranghello, RP Ribas, AI Reis
pp (1-4), 55-58, 2009
32009
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Articles 1–20