| Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors Y Kim, R Daly, J Kim, C Fallin, JH Lee, D Lee, C Wilkerson, K Lai, O Mutlu ACM SIGARCH Computer Architecture News 42 (3), 361-372, 2014 | 748 | 2014 |
| A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking JS Kim, CS Oh, H Lee, D Lee, HR Hwang, S Hwang, B Na, J Moon, ... IEEE Journal of Solid-State Circuits 47 (1), 107-116, 2011 | 343 | 2011 |
| A case for exploiting subarray-level parallelism (SALP) in DRAM Y Kim, V Seshadri, D Lee, J Liu, O Mutlu 2012 39th Annual International Symposium on Computer Architecture (ISCA …, 2012 | 329 | 2012 |
| RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization V Seshadri, Y Kim, C Fallin, D Lee, R Ausavarungnirun, G Pekhimenko, ... Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 286 | 2013 |
| Tiered-latency DRAM: A low latency and low cost DRAM architecture D Lee, Y Kim, V Seshadri, J Liu, L Subramanian, O Mutlu 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 276 | 2013 |
| Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology V Seshadri, D Lee, T Mullins, H Hassan, A Boroumand, J Kim, MA Kozuch, ... 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017 | 219 | 2017 |
| Improving DRAM performance by parallelizing refreshes with accesses KKW Chang, D Lee, Z Chishti, AR Alameldeen, C Wilkerson, Y Kim, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 196 | 2014 |
| Adaptive-latency DRAM: Optimizing DRAM timing for the common-case D Lee, Y Kim, G Pekhimenko, S Khan, V Seshadri, K Chang, O Mutlu 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 186 | 2015 |
| The efficacy of error mitigation techniques for DRAM retention failures: A comparative experimental study S Khan, D Lee, Y Kim, AR Alameldeen, C Wilkerson, O Mutlu ACM SIGMETRICS Performance Evaluation Review 42 (1), 519-532, 2014 | 175 | 2014 |
| Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization KK Chang, A Kashyap, H Hassan, S Ghose, K Hsieh, D Lee, T Li, ... Proceedings of the 2016 ACM SIGMETRICS International Conference on …, 2016 | 149 | 2016 |
| Fast bulk bitwise AND and OR in DRAM V Seshadri, K Hsieh, A Boroum, D Lee, MA Kozuch, O Mutlu, PB Gibbons, ... IEEE Computer Architecture Letters 14 (2), 127-131, 2015 | 148 | 2015 |
| Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM KK Chang, PJ Nair, D Lee, S Ghose, MK Qureshi, O Mutlu 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 143 | 2016 |
| ChargeCache: Reducing DRAM latency by exploiting row access locality H Hassan, G Pekhimenko, N Vijaykumar, V Seshadri, D Lee, O Ergin, ... 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 131 | 2016 |
| Simultaneous multi-layer access: Improving 3D-stacked memory bandwidth at low cost D Lee, S Ghose, G Pekhimenko, S Khan, O Mutlu ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-29, 2016 | 120 | 2016 |
| Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017 | 114 | 2017 |
| The blacklisting memory scheduler: Achieving high performance and fairness at low cost L Subramanian, D Lee, V Seshadri, H Rastogi, O Mutlu 2014 IEEE 32nd International Conference on Computer Design (ICCD), 8-15, 2014 | 108 | 2014 |
| Decoupled direct memory access: Isolating CPU and IO traffic by leveraging a dual-data-port DRAM D Lee, L Subramanian, R Ausavarungnirun, J Choi, O Mutlu 2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015 | 107 | 2015 |
| Multipath accessible semiconductor memory device with host interface between processors S Yun-Hee, H Sohn, Y Lee, D Lee, J Park, H Lee, M Kim, J Kim, C Lee US Patent 7,941,612, 2011 | 106 | 2011 |
| PARBOR: An efficient system-level technique to detect data-dependent failures in DRAM S Khan, D Lee, O Mutlu 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016 | 99 | 2016 |
| Accelerating read mapping with FastHASH H Xin, D Lee, F Hormozdiari, S Yedkar, O Mutlu, C Alkan BMC genomics 14 (1), 1-13, 2013 | 95 | 2013 |
Onur MutluETH Zürich and Carnegie Mellon UniversityVerified email at inf.ethz.ch
