| Computational aspects of optical lithography extension by directed self-assembly K Lai, C Liu, J Pitera, DJ Dechene, A Schepis, J Abdallah, H Tsai, ... Optical Microlithography XXVI 8683, 868304, 2013 | 32 | 2013 |
| Towards electrical testable SOI devices using Directed Self-Assembly for fin formation CC Liu, C Estrada-Raygoza, H He, M Cicoria, V Rastogi, N Mohanty, ... Alternative Lithographic Technologies VI 9049, 35-46, 2014 | 30 | 2014 |
| Computational lithography platform for 193i-guided directed self-assembly K Lai, M Ozlem, JW Pitera, C Liu, A Schepis, D Dechene, A Krasnoperova, ... Optical Microlithography XXVII 9052, 361-372, 2014 | 16 | 2014 |
| Directed self-assembly process implementation in a 300mm pilot line environment CC Liu, IC Estrada-Raygoza, J Abdallah, S Holmes, Y Yin, A Schepis, ... Alternative Lithographic Technologies V 8680, 322-329, 2013 | 15 | 2013 |
| Study of angular effects for optical systems into the EUV A Burbine, Z Levinson, A Schepis, BW Smith Extreme Ultraviolet (EUV) Lithography V 9048, 663-669, 2014 | 6 | 2014 |
| Optimization of image-based aberration metrology for EUV lithography Z Levinson, G Fenger, A Burbine, AR Schepis, BW Smith Extreme Ultraviolet (EUV) Lithography V 9048, 655-662, 2014 | 4 | 2014 |
| Method for die-level unique authentication and serialization of semiconductor devices A Schepis, AJ Devilliers, HJ Fulford US Patent App. 16/528,043, 2020 | 2 | 2020 |
| Cyclic self-limiting etch process AR Schepis, H Kang US Patent 11,791,167, 2023 | 1 | 2023 |
| Localized stress regions for three-dimension chiplet formation AJ Devilliers, DJ Fulford, AR Schepis, MI Gardner, HJ Fulford US Patent 11,721,551, 2023 | 1 | 2023 |
| Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking HJ Fulford, A Schepis, AJ Devilliers US Patent 11,133,206, 2021 | 1 | 2021 |
| Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking HJ Fulford, A Schepis, AJ Devilliers US Patent 11,862,497, 2024 | | 2024 |
| Method of patterning a substrate using a sidewall spacer etch mask J Grzeskowiak, A Schepis, A Devilliers US Patent App. 18/354,388, 2023 | | 2023 |
| Method for chuck compensation via wafer shape control AR Schepis, DJ Fulford, DC Conklin, AJ Devilliers US Patent App. 17/967,257, 2023 | | 2023 |
| Wafer shape control for w2w bonding AR Schepis, A Weloth, DC Conklin, AJ Devilliers US Patent App. 17/885,097, 2023 | | 2023 |
| Hybrid patterning-bonding semiconductor tool AR Schepis, A Weloth, DC Conklin, AJ Devilliers US Patent App. 17/885,038, 2023 | | 2023 |
| Method of patterning a substrate using a sidewall spacer etch mask J Grzeskowiak, A Schepis, A Devilliers US Patent 11,782,346, 2023 | | 2023 |
| Planarization of spin-on films AR Schepis, A Devilliers US Patent 11,776,808, 2023 | | 2023 |
| In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones DJ Fulford, AR Schepis, MI Gardner, HJ Fulford, AJ Devilliers US Patent App. 17/889,460, 2023 | | 2023 |
| Method to enhance lithography pattern creation using semiconductor stress film tuning AR Schepis, DJ Fulford, MI Gardner, HJ Fulford, AJ Devilliers US Patent App. 17/890,766, 2023 | | 2023 |
| Localized stress regions for three-dimension chiplet formation AJ Devilliers, DJ Fulford, AR Schepis, MI Gardner, HJ Fulford US Patent 11,688,642, 2023 | | 2023 |
