| Dynamic semiconductor memory device T Fujino, K Arimoto US Patent 6,151,244, 2000 | 411 | 2000 |
| Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for … K Arimoto, H Shimano, T Fujino, T Hashizume US Patent 6,449,204, 2002 | 103 | 2002 |
| Reversing stealthy dopant-level circuits T Sugawara, D Suzuki, R Fujii, S Tawa, R Hori, M Shiozaki, T Fujino Cryptographic Hardware and Embedded Systems–CHES 2014: 16th International …, 2014 | 92 | 2014 |
| Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement T Tanizaki, M Kinoshita, T Fujino, T Tsuruda, F Morishita, T Amano, ... US Patent 6,064,621, 2000 | 73 | 2000 |
| On measurable side-channel leaks inside ASIC design primitives T Sugawara, D Suzuki, M Saeki, M Shiozaki, T Fujino Cryptographic Hardware and Embedded Systems-CHES 2013: 15th International …, 2013 | 58 | 2013 |
| Semiconductor memory device suitable for merging with logic N Watanabe, A Yamazaki, K Arimoto, T Fujino, I Hayashi, H Noda US Patent 6,418,067, 2002 | 54 | 2002 |
| Deep learning side-channel attack against hardware implementations of AES T Kubota, K Yoshida, M Shiozaki, T Fujino Microprocessors and Microsystems 87, 103383, 2021 | 52 | 2021 |
| Hierarchical image-scrambling method with scramble-level controllability for privacy protection T Honda, Y Murakami, Y Yanagihara, T Kumaki, T Fujino 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 51 | 2013 |
| The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement K Fruhashi, M Shiozaki, A Fukushima, T Murayama, T Fujino 2011 IEEE international symposium of circuits and systems (ISCAS), 2325-2328, 2011 | 51 | 2011 |
| Semiconductor memory device capable of increasing chip yields while maintaining rapid operation M Kobayashi, T Tanizaki, K Arimoto, T Amano, T Fujino, T Tsuruda, ... US Patent 5,914,907, 1999 | 47 | 1999 |
| Disabling backdoor and identifying poison data by using knowledge distillation in backdoor attacks on deep neural networks K Yoshida, T Fujino Proceedings of the 13th ACM workshop on artificial intelligence and security …, 2020 | 44 | 2020 |
| Tamper-resistant memory integrated circuit and encryption circuit using same T Fujino US Patent 8,861,720, 2014 | 40 | 2014 |
| Refresh-free dynamic semiconductor memory device K Arimoto, H Shimano, T Fujino, T Hashizume US Patent 6,925,022, 2005 | 38 | 2005 |
| Model-extraction attack against FPGA-DNN accelerator utilizing correlation electromagnetic analysis K Yoshida, T Kubota, M Shiozaki, T Fujino 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019 | 37 | 2019 |
| Sputtered w-ti film for x-ray mask absorber H Yabe, K Marumoto, S Aya, N Yoshioka, T Fujino, Y Watakabe, ... Japanese journal of applied physics 31 (12S), 4210, 1992 | 33 | 1992 |
| Refresh-free dynamic semiconductor memory device K Arimoto, H Shimano, T Fujino, T Hashizume US Patent 7,139,208, 2006 | 31 | 2006 |
| Semiconductor memory device having row-related circuit operating at high speed T Fujino, K Inoue, A Yamazaki, K Arimoto US Patent 6,507,532, 2003 | 29 | 2003 |
| 0.15/spl mu/m CMOS process for high performance and high reliability S Shimizu, T Kuroi, M Kobayashi, T Yamaguchi, T Fujino, H Maeda, ... Proceedings of 1994 IEEE International Electron Devices Meeting, 67-70, 1994 | 29 | 1994 |
| Model reverse-engineering attack using correlation power analysis against systolic array based neural network accelerator K Yoshida, T Kubota, S Okura, M Shiozaki, T Fujino 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 28 | 2020 |
| A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications M Taniguchi, M Shiozaki, H Kubo, T Fujino 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE), 525-527, 2013 | 28 | 2013 |
