Pablo Abad
Pablo Abad
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TítuloCitado porAño
Rotary router: an efficient architecture for CMP interconnection networks
P Abad, V Puente, JA Gregorio, P Prieto
ACM SIGARCH Computer Architecture News 35 (2), 116-125, 2007
1062007
Topaz: An open-source interconnection network simulator for chip multiprocessors and supercomputers
P Abad, P Prieto, LG Menezo, A Colaso, V Puente, JÁ Gregorio
Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on, 99-106, 2012
862012
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks
P Abad, V Puente, JA Gregorio
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
672009
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors
P Abad, V Puente, JA Gregorio
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 37, 2013
122013
Balancing performance and cost in CMP interconnection networks
P Abad, V Puente, JA Gregorio
IEEE Transactions on Parallel and Distributed Systems 23 (3), 452-459, 2012
102012
Reducing the interconnection network cost of chip multiprocessors
P Abad, V Puente, JÁ Gregorio
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 183-192, 2008
102008
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of an Non-volatile Endurance-limited Main Memory
P Abad, P Prieto, V Puente, JA Gregorio
Transactions on Parallel and Distributed Systems, 2015
92015
Adaptive-Tree Multicast: Efficient Multi-destination Support for CMP Communication Substrate
P Abad, V Puente, L Menezo, J Gregorio
IEEE, 2012
62012
Improving coherence protocol reactiveness by trading bandwidth for latency
LG Menezo, V Puente, P Abad, JÁ Gregorio
Proceedings of the 9th conference on Computing Frontiers, 143-152, 2012
42012
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation
A Colaso, P Prieto, JA Herrero, P Abad, LG Menezo, V Puente, ...
IEEE Transactions on Parallel and Distributed Systems 29 (5), 1161-1173, 2018
32018
Improving Last Level Shared Cache Performance through Mobile Insertion Policies (MIP)
P Abad, P Prieto, V Puente, JA Gregorio
Parallel Computing 49 (C), 13-27, 2015
32015
Interaction of NoC design and Coherence Protocol in 3D-stacked CMPs
P Abad, P Prieto, LG Menezo, A Colaso, V Puente, JA Gregorio
16th Euromicro Conference on Digital System Design, 48-55, 2013
22013
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation
A Colaso, P Prieto, JA Herrero, P Abad, V Puente, JA Gregorio
arXiv preprint arXiv:1902.02837, 2019
12019
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip
P Abad, P Prieto, V Puente, JA Gregorio
2012 IEEE 30th International Conference on Computer Design (ICCD), 55-60, 2012
12012
Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms
A Colaso, P Prieto, P Abad, JA Gregorio, V Puente
2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019
2019
Mosaic: A Scalable Coherence Protocol
LG Menezo, V Puente, P Abad, JA Gregorio
International Journal of Parallel Programming 46 (6), 1110-1138, 2018
2018
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