Konstantinos Tatas
Konstantinos Tatas
Verified email at frederick.ac.cy - Homepage
Title
Cited by
Cited by
Year
Designing 2D and 3D network-on-chip architectures
K Tatas, K Siozios, D Soudris, A Jantsch
Springer, 2014
622014
Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications
D Soudris, ND Zervas, A Argyriou, M Dasygenis, K Tatas, CE Goutis, ...
International Workshop on Power and Timing Modeling, Optimization and …, 2000
492000
DAGGER: A novel generic methodology for FPGA bitstream generation and its software tool implementation
K Siozios, G Koutroumpezis, K Tatas, D Soudris, A Thanailakis
19th IEEE International Parallel and Distributed Processing Symposium, 4 pp., 2005
242005
An integrated framework for architecture level exploration of reconfigurable platform
K Siozios, K Tatas, G Koutroumpezis, D Soudris, A Thanailakis
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
212005
Power and performance exploration of embedded systems executing multimedia kernels
M Dasygenis, N Kroupis, K Tatas, A Argyriou, D Soudris, A Thanailakis
IEE Proceedings-Computers and Digital Techniques 149 (4), 164-172, 2002
152002
A novel FPGA architecture and an integrated framework of CAD tools for implementing applications
K Siozios, G Koutroumpezis, K Tatas, N Vassiliadis, V Kalenteridis, ...
IEICE transactions on information and systems 88 (7), 1369-1380, 2005
142005
An integrated FPGA design framework: Custom designed FPGA platform and application mapping toolset development
V Kalenteridis, H Pournara, K Siozios, K Tatas, G Koytroympezis, ...
18th International Parallel and Distributed Processing Symposium, 2004 …, 2004
142004
A memory management approach for efficient implementation of multimedia kernels on programmable architectures
M Dasigenis, N Kroupis, A Argyriou, K Tatas, D Soudris, A Thanailakis, ...
Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001
132001
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications
K Tatas, G Koutroumpezis, D Soudris, A Thanailakis
Integration 40 (2), 74-93, 2007
122007
A survey of existing fine-grain reconfigurable architectures and CAD tools
K Tatas, K Siozios, D Soudris
Fine-and Coarse-Grain Reconfigurable Computing, 3-87, 2007
122007
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware
V Kalenteridis, H Pournara, K Siozos, K Tatas, N Vassiliadis, I Pappas, ...
Microprocessors and Microsystems 29 (6), 247-259, 2005
112005
A novel FPGA configuration bitstream generation algorithm and tool development
K Siozios, G Koutroumpezis, K Tatas, D Soudris, A Thanailakis
International Conference on Field Programmable Logic and Applications, 1116-1118, 2004
102004
FPGA architecture design and toolset for logic implementation
K Tatas, K Siozios, N Vasiliadis, DJ Soudris, S Nikolaidis, S Siskos, ...
International Workshop on Power and Timing Modeling, Optimization and …, 2003
102003
A full adder based methodology for scaling operation in residue number system
D Soudris, M Dasygenis, K Mitroglou, K Tatas, A Thanailakis
9th International Conference on Electronics, Circuits and Systems 3, 891-894, 2002
92002
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems
D Soudris, K Sgouropoulos, K Tatas, V Pavlidis, A Thanailakis
Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003
82003
Data and instruction memory exploration of embedded systems for multimedia applications
M Dasigenis, N Kroupis, A Argyriou, K Tatas, D Soudris, N Zervas
2001 IEEE International Conference on Acoustics, Speech, and Signal …, 2001
72001
Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip
K Tatas, C Chrysostomou
Microprocessors and Microsystems 52, 80-88, 2017
62017
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications
K Siozios, K Tatas, D Soudris, A Thanailakis
Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006
62006
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow
D Soudris, S Nikolaidis, S Siskos, K Tatas, K Siozios, G Koutroumpezis, ...
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation …, 2005
62005
Power optimization methodology for multimedia applications implementation on reconfigurable platforms
K Tatas, K Siozios, D Soudris, K Masselos, K Potamianos, S Blionas, ...
International Workshop on Power and Timing Modeling, Optimization and …, 2003
52003
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