Kenzo Van Craeynest
Kenzo Van Craeynest
Verified email at elis.ugent.be
Title
Cited by
Cited by
Year
Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)
K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer
Proceedings of the 39th International Symposium on Computer Architecture …, 2012
3472012
Fairness-aware scheduling on single-ISA heterogeneous multi-cores
K Van Craeynest, S Akram, W Heirman, A Jaleel, L Eeckhout
Parallel Architectures and Compilation Techniques (PACT), 2013 22nd …, 2013
892013
BarrierPoint: Sampled Simulation of Multi-Threaded Applications
TE Carlson, W Heirman, K Van Craeynest, L Eeckhout
Proceedings of the IEEE International Symposium on Performance Analysis of …, 2014
402014
Understanding fundamental design choices in single-ISA heterogeneous multicore architectures
K Van Craeynest, L Eeckhout
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 32, 2013
362013
Undersubscribed Threading on Clustered Cache Architectures
W Heirman, TE Carlson, K Van Craeynest, I Hur, A Jaleel, L Eeckhout
27*
PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM
B GINZBURG, I OSADCHIY, R RONEN, E WEISSMANN, M MISHAELI, ...
WO Patent 2,013,101,139, 2013
23*2013
The Multi-Program Performance Model: Debunking current practice in multi-core simulation
K Van Craeynest, L Eeckhout
Workload Characterization (IISWC), 2011 IEEE International Symposium on, 26-37, 2011
202011
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor
W Heirman, TE Carlson, K Van Craeynest, I Hur, A Jaleel, L Eeckhout
Proceedings of the 4th International Workshop on Runtime and Operating …, 2014
122014
MLP-Aware runahead threads in a simultaneous multithreading processor
K Van Craeynest, S Eyerman, L Eeckhout
High Performance Embedded Architectures and Compilers, 110-124, 2009
122009
Modeling and scheduling heterogeneous multi-core architectures
K Van Craeynest
Ghent University, 2013
2013
Optimaliseren van geheugenparallellisme in een SMT processor.
K Van Craeynest
2007
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Articles 1–11