| A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 17 | 2022 |
| A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking … SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 57 (12), 3538-3551, 2022 | 8 | 2022 |
| A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 5 | 2022 |
| Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs A Iesurum, D Manente, F Padovan, M Bassi, A Bevilacqua IEEE Journal of Solid-State Circuits, 2023 | 4 | 2023 |
| A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 58 (3), 634-646, 2022 | 3 | 2022 |
| A 24 GHz Quadrature VCO Based on Coupled PLL with-134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS A Iesurum, D Manente, F Padovan, M Bassi, A Bevilacqua ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 3 | 2022 |
| Analysis and Design of mm-Wave Harmonic Oscillators in CMOS Technology A Iesurum Università degli studi di Padova, 2024 | | 2024 |
