Alejandro Rico
TítuloCitado porAño
Task superscalar: An out-of-order task pipeline
Y Etsion, F Cabarcas, A Rico, A Ramirez, RM Badia, E Ayguade, ...
Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on …, 2010
Tibidabo: Making the case for an ARM-based HPC system
N Rajovic, A Rico, N Puzovic, C Adeniyi-Jones, A Ramirez
Future Generation Computer Systems 36, 322-334, 2014
Trace-driven simulation of multithreaded applications
A Rico, A Duran, F Cabarcas, Y Etsion, A Ramirez, M Valero
Performance Analysis of Systems and Software (ISPASS), 2011 IEEE …, 2011
On the simulation of large-scale architectures using multiple application abstraction levels
A Rico, F Cabarcas, C Villavieja, M Pavlovic, A Vega, Y Etsion, A Ramirez, ...
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 36, 2012
Experiences with mobile processors for energy efficient HPC
N Rajovic, A Rico, J Vipond, I Gelado, N Puzovic, A Ramirez
Proceedings of the Conference on Design, Automation and Test in Europe, 464-468, 2013
Criticality-aware dynamic task scheduling for heterogeneous architectures
K Chronaki, A Rico, RM Badia, E Ayguadé, J Labarta, M Valero
Proceedings of the 29th ACM on International Conference on Supercomputing …, 2015
The mont-blanc prototype: An alternative approach for hpc systems
N Rajovic, A Rico, F Mantovani, D Ruiz, JO Vilarrubi, C Gomez, L Backes, ...
High Performance Computing, Networking, Storage and Analysis, SC16 …, 2016
Scalable simulation of decoupled accelerator architectures
A Rico, F Cabarcas, A Quesada, M Pavlovic, AJ Vega, C Villavieja, ...
Universitat Politecnica de Catalunya, Tech. Rep. UPC-DACRR-2010-14, 2010
The ARM Scalable Vector Extension
N Stephens, S Biles, M Boettcher, J Eapen, M Eyole, G Gabrielli, ...
IEEE Micro 37 (2), 26-39, 2017
Task Scheduling Techniques for Asymmetric Multi-core Systems
K Chronaki, A Rico, M Casas, M Moretó, RM Badia, E Ayguadé, J Labarta, ...
IEEE Transactions on Parallel and Distributed Systems 28 (7), 2074-2087, 2017
Available task-level parallelism on the Cell BE
A Rico, A Ramirez, M Valero
Scientific Programming 17 (1-2), 59-76, 2009
Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications
V García, J Gomez-Luna, T Grass, A Rico, E Ayguade, AJ Pena
Workload Characterization (IISWC), 2016 IEEE International Symposium on, 1-10, 2016
TaskPoint: Sampled Simulation of Task-Based Programs
T Grass, A Rico, M Casas, M Moreto, E Ayguadé
Performance Analysis of Systems and Software (ISPASS), 2016 IEEE …, 2016
MUSA: a multi-level simulation approach for next-generation HPC machines
T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ...
Proceedings of the International Conference for High Performance Computing …, 2016
Interleaving granularity on high bandwidth memory architecture for CMPs
F Cabarcas, A Rico, Y Etsion, A Ramirez
Embedded Computer Systems (SAMOS), 2010 International Conference on, 250-257, 2010
Cellsim: A validated modular heterogeneous multiprocessor simulator
F Cabarcas, A Rico, D Rodenas, X Martorell, Á Ramírez, E Ayguade
XVIII Jornadas de paralelismo, 181-188, 2006
Experiences in speeding up computer vision applications on mobile computing platforms
L Backes, A Rico, B Franke
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS …, 2015
Comparing last-level cache designs for CMP architectures
A Vega, A Rico, F Cabarcas, A Ramirez, M Valero
Proceedings of the Second International Forum on Next-Generation Multicore …, 2010
CellSim: A Cell Processor Simulation Infrastructure
F Cabarcas, A Rico, D Rodenas, X Martorell, A Ramirez, E Ayguade
HiPEAC ACACES-2007, 279-282, 2007
A module-based cell processor simulator
F Cabarcas Jaramillo, A Rico Carro, D Rodenas, X Martorell Bofill, ...
ACACES 2006: poster abstracts: July 26, 2006, L'Aquila, Italy, 237-240, 2006
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Artículos 1–20