David Trilla
Title
Cited by
Cited by
Year
Cache side-channel attacks and time-predictability in high-performance critical real-time systems
D Trilla, C Hernandez, J Abella, FJ Cazorla
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
162018
Improving early design stage timing modeling in multicore based real-time systems
D Trilla, J Jalle, M Fernandez, J Abella, FJ Cazorla
2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2016
72016
Resilient random modulo cache memories for probabilistically-analyzable real-time systems
D Trilla, C Hernandez, J Abella, FJ Cazorla
2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016
52016
Aging Assessment and Design Enhancement of Randomized Cache Memories
D Trilla, C Hernandez, J Abella, FJ Cazorla
IEEE Transactions on Device and Materials Reliability 17 (1), 32-41, 2017
22017
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices
D Trilla, C Hernandez, J Abella, FJ Cazorla
IEEE Transactions on Sustainable Computing, 2019
12019
De-RISC–Dependable Real-Time Infrastructure for Safety-Critical Computer Systems
F Gómez, M Masmano, V Nicolau, J Andersson, J Le Rhun, D Trilla, ...
ADA USER 41 (2), 107, 2020
2020
Multi-Vehicle Map Fusion using GNU Radio
EA Sisbot, A Vega, A Paidimarri, JD Wellman, A Buyuktosunoglu, P Bose, ...
Proceedings of the GNU Radio Conference 4 (1), 2019
2019
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior
D Trilla, C Hernández, J Abella, FJ Cazorla
2019 22nd Euromicro Conference on Digital System Design (DSD), 538-545, 2019
2019
Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation
D Trilla, C Hernández, J Abella, FJ Cazorla
2019 22nd Euromicro Conference on Digital System Design (DSD), 601-605, 2019
2019
Randomization for safer, more reliable and secure, high-performance automotive processors
D Trilla, FJ Cazorla, C Hernandez, J Abella
IEEE Design & Test 36 (6), 39-47, 2019
2019
Modelling bus contention during system early design stages
D Trilla, C Hernandez, J Abella, FJ Cazorla
2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES …, 2017
2017
On the suitability of time-randomized processors for secure and reliable high-performance computing
D Trilla, C Hernandez, J Abella Ferrer, FJ Cazorla Almeida
Book of abstracts, 110-113, 2017
2017
Time-randomized Processors for Secure and Reliable High-Performance Computing
D Trilla, C Hernández
Four birds with one stone: On the use of time-randomized processors to address the time-predictability, reliability, energy and security challenges of real-time autonomous systems
D Trilla, C Hernandez, J Abella, FJ Cazorla
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Articles 1–14