Spin logic devices via electric field controlled magnetization reversal by spin-orbit torque M Yang, Y Deng, Z Wu, K Cai, KW Edmonds, Y Li, Y Sheng, S Wang, ... IEEE Electron Device Letters 40 (9), 1554-1557, 2019 | 82 | 2019 |
Mobility enhancement technology for scaling of CMOS devices: overview and status Y Song, H Zhou, Q Xu, J Luo, H Yin, J Yan, H Zhong Journal of electronic materials 40, 1584-1612, 2011 | 81 | 2011 |
Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor H Yin, J Luo, H Zhu, Z Luo US Patent 8,835,316, 2014 | 78 | 2014 |
Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1− xPtx silicide films J Luo, Z Qiu, C Zha, Z Zhang, D Wu, J Lu, J Åkerman, M Östling, ... Applied Physics Letters 96 (3), 2010 | 62 | 2010 |
Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation X Yin, Y Zhang, H Zhu, GL Wang, JJ Li, AY Du, C Li, LH Zhao, WX Huang, ... IEEE Electron Device Letters 41 (1), 8-11, 2019 | 56 | 2019 |
Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology G Wang, A Abedin, M Moeen, M Kolahdouz, J Luo, Y Guo, T Chen, H Yin, ... Solid-State Electronics 103, 222-228, 2015 | 53 | 2015 |
Interaction of NiSi with dopants for metallic source/drain applications J Luo, ZJ Qiu, Z Zhang, M Östling, SL Zhang Journal of Vacuum Science & Technology B 28 (1), C1I1-C1I11, 2010 | 42 | 2010 |
Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS) GL Wang, M Moeen, A Abedin, M Kolahdouz, J Luo, CL Qin, HL Zhu, ... Journal of Applied Physics 114 (12), 2013 | 41 | 2013 |
FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin Q Zhang, H Yin, J Luo, H Yang, L Meng, Y Li, Z Wu, Y Zhang, Y Zhang, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.3. 1-17.3. 4, 2016 | 39 | 2016 |
Application of atomic layer deposition tungsten (ALD W) as gate filling metal for 22 nm and beyond nodes CMOS technology G Wang, Q Xu, T Yang, J Xiang, J Xu, J Gao, C Li, J Li, J Yan, D Chen, ... ECS Journal of Solid State Science and Technology 3 (4), P82, 2014 | 39 | 2014 |
Ultra-shallow junctions formed using microwave annealing P Xu, C Fu, C Hu, D Wei Zhang, D Wu, J Luo, C Zhao, ZB Zhang, ... Applied Physics Letters 102 (12), 2013 | 39 | 2013 |
Optimization of structure and electrical characteristics for four-layer vertically-stacked horizontal gate-all-around Si nanosheets devices Q Zhang, J Gu, R Xu, L Cao, J Li, Z Wu, G Wang, J Yao, Z Zhang, J Xiang, ... Nanomaterials 11 (3), 646, 2021 | 36 | 2021 |
CMOS past, present and future H Radamson, E Simoen, J Luo, C Zhao Woodhead Publishing, 2018 | 35 | 2018 |
Effects of defects and thermal treatment on the properties of graphene K Jia, Y Su, Y Chen, J Luo, J Yang, P Lv, Z Zhang, H Zhu, C Zhao, T Ye Vacuum 116, 90-95, 2015 | 35 | 2015 |
Design impact on the performance of Ge PIN photodetectors X Zhao, M Moeen, MS Toprak, G Wang, J Luo, X Ke, Z Li, D Liu, W Wang, ... Journal of Materials Science: Materials in Electronics 31, 18-25, 2020 | 33 | 2020 |
Effect of hydrogen carrier gas on AlN and AlGaN growth in AMEC Prismo D-Blue® MOCVD platform Q Bao, T Zhu, N Zhou, S Guo, J Luo, C Zhao Journal of Crystal Growth 419, 52-56, 2015 | 33 | 2015 |
Effects of carbon on Schottky barrier heights of NiSi modified by dopant segregation J Luo, ZJ Qiu, DW Zhang, PE Hellstrom, M Ostling, SL Zhang IEEE electron device letters 30 (6), 608-610, 2009 | 33 | 2009 |
Semiconductor structure and method for manufacturing the same H Yin, J Luo, H Zhu, Z Luo US Patent 8,642,471, 2014 | 30 | 2014 |
Mechanism of TMAl pre-seeding in AlN epitaxy on Si (111) substrate Q Bao, J Luo, C Zhao Vacuum 101, 184-188, 2014 | 29 | 2014 |
Semiconductor FET and Method for Manufacturing the Same C Zhao, J Luo, H Zhong US Patent App. 13/697,319, 2013 | 28 | 2013 |