Pedro P. Carballo
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Casse: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip
V Reyes, T Bautista, G Marrero, PP Carballo, W Kruijtzer
Euromicro Symposium on Digital System Design, 2004. DSD 2004., 476-483, 2004
462004
Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation
K Eshraghian, R Sarmiento, PP Carballo, A Núnez
Microprocessing and Microprogramming 32 (1-5), 75-82, 1991
291991
High speed primitives of hardware accelerators for DSP in GaAs technology
R Sarmiento, PP Carballo, A Núnez
IEE Proceedings G (Circuits, Devices and Systems) 139 (2), 205-216, 1992
271992
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
A Domínguez, PP Carballo, A Núñez
2017 12th International Symposium on Reconfigurable Communication-centric …, 2017
102017
Scalable video coding deblocking filter FPGA and ASIC implementation using high-level synthesis methodology
PP Carballo, O Espino, R Neris, P Hernández-Fernández, TM Szydzik, ...
2013 Euromicro Conference on Digital System Design, 415-422, 2013
72013
Rapid-prototyping of high-performance RISC cores with VHDL
T Bautista, G Marrero, PP Carballo, A Nunez
Proceedings VHDL International Users' Forum. Fall Conference, 43-52, 1997
71997
ESL flow for a hardware H. 264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study
M Thadani, PP Carballo, P Hernández, G Marrero, A Núñez
VLSI Circuits and Systems IV 7363, 73630K, 2009
62009
Towards a low-cost processor architecture for multimedia
T Bautista, G Marrero, PP Carballo, A Núñez
XI Conference of Design of Integrated Circuits and Systems 647, 445-450, 1996
41996
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems
A Sánchez-Peña, PP Carballo, L García, A Núñez
9th EUROMICRO Conference on Digital System Design (DSD'06), 305-312, 2006
22006
Setting up a full-custom design environment on cadence for GaAs technology.
P Carballo, J Montiel, R Sarmiento, A Nunez
21994
Some results in GaAs processor design using LSI integrated circuits
A Núñez, R Sarmiento, PP Carballo
Microprocessing and Microprogramming 25 (1-5), 127-132, 1989
11989
Design and Implementation of a TCP/IP packet filter and classifier IP block through High Level Synthesis
BV del Pino, PP Carballo, A Nuñez
IUMA, Institute for Applied Microelectronics, University of Las Palmas Gran …, 0
1
Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs
R León, A Domínguez, PP Carballo, A Núñez
2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2019
2019
TCP/IP Packet Analyzer on a Zynq Platform
B Vega, P P. Carballo, P Hernández-Fernández, A Domínguez, A Núñez
Euromicro DSD/SEAA 2015, 2015
2015
Implementation of scalable video coding deblocking filter from high-level SystemC description
PP Carballo, O Espino, R Neris, P Hernández-Fernández, TM Szydzik, ...
VLSI Circuits and Systems VI 8764, 876408, 2013
2013
DSD 2009
A Nunez, PP Carballo
2009
Accelerating a MPEG-4 video decoder through custom software/hardware co-design
JL Díaz, D Barreto, L García, G Marrero, PP Carballo, A Núñez
VLSI Circuits and Systems III 6590, 65900B, 2007
2007
Exploring system interconnection architectures with VIPACES: from direct connections to NoCs
A Sánchez-Peña, PP Carballo, A Núñez
VLSI Circuits and Systems III 6590, 65900Q, 2007
2007
Exploring system interconnection architectures with VIPACES: from direct connections to NoCs [6590-18]
A Sanchez-Pena, PP Carballo, A Nunez
PROCEEDINGS-SPIE THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING 6590, 6590, 2007
2007
Accelerating a MPEG-4 video decoder through custom software/hardware co-design [6590-07]
JL Diaz, D Barreto, L Garcia, G Marrero, PP Carballo, A Nunez
PROCEEDINGS-SPIE THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING 6590, 6590, 2007
2007
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Artículos 1–20