Computer Architecture Research Group of the University of Zaragoza
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Delaying physical register allocation through virtual-physical registers
T Monreal, A González, M Valero, J González, V Viñals
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999
SigRace: signature-based data race detection
A Muzahid, D Suárez, S Qi, J Torrellas
ACM SIGARCH Computer Architecture News 37 (3), 337-348, 2009
The promise of reconfigurable computing for hyperspectral imaging onboard systems: A review and trends
S Lopez, T Vladimirova, C Gonzalez, J Resano, D Mozos, A Plaza
Proceedings of the IEEE 101 (3), 698-722, 2013
Design, fabrication, and characterization of a submicroelectromechanical resonator with monolithically integrated CMOS readout circuit
J Verd, G Abadal, J Teva, MV Gaudó, A Uranga, X Borrisé, F Campabadal, ...
Journal of microelectromechanical systems 14 (3), 508-519, 2005
A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware [multimedia applications]
J Resano, D Mozos, F Catthoor
Design, Automation and Test in Europe, 106-111, 2005
Zeolite-modified cantilevers for the sensing of nitrotoluene vapors
MA Urbiztondo, I Pellejero, M Villarroya, J Sesé, MP Pina, I Dufour, ...
Sensors and Actuators B: Chemical 137 (2), 608-616, 2009
Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing
C Gonzalez, S Sánchez, A Paz, J Resano, D Mozos, A Plaza
INTEGRATION, the VLSI journal 46 (2), 89-103, 2013
A reconfigurable manager for dynamically reconfigurable hardware
J Resano, D Mozos, D Verkest, F Catthoor
IEEE Design & Test of Computers 22 (5), 452-460, 2005
FPGA implementation of the N-FINDR algorithm for remotely sensed hyperspectral image analysis
C González, D Mozos, J Resano, A Plaza
IEEE transactions on geoscience and remote sensing 50 (2), 374-388, 2011
El teletrabajo
J Thibault Aranda, JL Briz Velasco, JL Fandos, JM Álvarez López
Acciones e investigaciones sociales, 0203-233, 1998
The reuse cache: downsizing the shared last-level cache
J Albericio, P Ibáñez, V Viñals, JM Llabería
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
System on chip mass sensor based on polysilicon cantilevers arrays for multiple detection
M Villarroya, J Verd, J Teva, G Abadal, E Forsen, FP Murano, A Uranga, ...
Sensors and Actuators A: Physical 132 (1), 154-164, 2006
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
MJ Garzarán, M Prvulovic, JM Llabería, V Viñals, L Rauchwerger, ...
ACM Transactions on Architecture and Code Optimization (TACO) 2 (3), 247-279, 2005
Hardware schemes for early register release
T Monreal, V Viñals, A González, M Valero
Proceedings International Conference on Parallel Processing, 5-13, 2002
FPGA implementation of abundance estimation for spectral unmixing of hyperspectral data using the image space reconstruction algorithm
C González, J Resano, A Plaza, D Mozos
IEEE Journal of Selected Topics in Applied Earth Observations and Remote …, 2011
A hardware implementation of a run-time scheduler for reconfigurable systems
JA Clemente, J Resano, C González, D Mozos
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (7 …, 2010
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware
J Resano, D Mozos
Proceedings of the 41st annual Design Automation Conference, 119-124, 2004
Store buffer design in first-level multibanked data caches
EF Torres, P Ibánez, V Viñals, JM Llabería
32nd International Symposium on Computer Architecture (ISCA'05), 469-480, 2005
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
A Valero, J Sahuquillo, S Petit, V Lorente, R Canal, P López, J Duato
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
Tradeoffs in buffering memory state for thread-level speculation in multiprocessors
MJ Garzarán, M Prvulovic, JM Llabería, V Viñals, L Rauchwerger, ...
The Ninth International Symposium on High-Performance Computer Architecture …, 2003
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