| El teletrabajo J Thibault Aranda, JL Briz Velasco, JL Fandos, JM Álvarez López Acciones e investigaciones sociales, 0203-233, 1998 | 180* | 1998 |
| Delaying physical register allocation through virtual-physical registers T Monreal, A González, M Valero, J González, V Viñals MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999 | 128 | 1999 |
| The promise of reconfigurable computing for hyperspectral imaging onboard systems: A review and trends S Lopez, T Vladimirova, C Gonzalez, J Resano, D Mozos, A Plaza Proceedings of the IEEE 101 (3), 698-722, 2013 | 125 | 2013 |
| SigRace: Signature-based data race detection A Muzahid, D Suárez, S Qi, J Torrellas Proceedings of the 36th annual international symposium on Computer …, 2009 | 122 | 2009 |
| Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing C Gonzalez, S Sánchez, A Paz, J Resano, D Mozos, A Plaza INTEGRATION, the VLSI journal 46 (2), 89-103, 2013 | 102 | 2013 |
| Design, fabrication, and characterization of a submicroelectromechanical resonator with monolithically integrated CMOS readout circuit J Verd, G Abadal, J Teva, MV Gaudó, A Uranga, X Borrisé, F Campabadal, ... Journal of microelectromechanical systems 14 (3), 508-519, 2005 | 100 | 2005 |
| El teletrabajo: Jornadas sobre Nuevos Empleos, Nuevas Empresas, Nuevas Relaciones Laborales J Thibault, JL Briz, JL Fandos, JM Alvarez Acciones e investigaciones sociales, 203-233, 1998 | 97* | 1998 |
| Zeolite-modified cantilevers for the sensing of nitrotoluene vapors MA Urbiztondo, I Pellejero, M Villarroya, J Sesé, MP Pina, I Dufour, ... Sensors and Actuators B: Chemical 137 (2), 608-616, 2009 | 95 | 2009 |
| A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware [multimedia applications] J Resano, D Mozos, F Catthoor Design, Automation and Test in Europe, 106-111, 2005 | 94 | 2005 |
| FPGA implementation of the N-FINDR algorithm for remotely sensed hyperspectral image analysis C González, D Mozos, J Resano, A Plaza IEEE transactions on geoscience and remote sensing 50 (2), 374-388, 2011 | 93 | 2011 |
| A reconfigurable manager for dynamically reconfigurable hardware J Resano, D Mozos, D Verkest, F Catthoor IEEE Design & Test of Computers 22 (5), 452-460, 2005 | 86 | 2005 |
| System on chip mass sensor based on polysilicon cantilevers arrays for multiple detection M Villarroya, J Verd, J Teva, G Abadal, E Forsen, FP Murano, A Uranga, ... Sensors and Actuators A: Physical 132 (1), 154-164, 2006 | 67 | 2006 |
| The reuse cache: downsizing the shared last-level cache J Albericio, P Ibáñez, V Viñals, JM Llabería 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013 | 66 | 2013 |
| FPGA implementation of abundance estimation for spectral unmixing of hyperspectral data using the image space reconstruction algorithm C González, J Resano, A Plaza, D Mozos IEEE Journal of Selected Topics in Applied Earth Observations and Remote …, 2011 | 65 | 2011 |
| A hardware implementation of a run-time scheduler for reconfigurable systems JA Clemente, J Resano, C González, D Mozos IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (7 …, 2010 | 64 | 2010 |
| Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors MJ Garzarán, M Prvulovic, JM Llabería, V Viñals, L Rauchwerger, ... ACM Transactions on Architecture and Code Optimization (TACO) 2 (3), 247-279, 2005 | 64 | 2005 |
| Hardware schemes for early register release T Monreal, V Viñals, A González, M Valero Proceedings International Conference on Parallel Processing, 5-13, 2002 | 62 | 2002 |
| Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware J Resano, D Mozos Proceedings of the 41st annual Design Automation Conference, 119-124, 2004 | 54 | 2004 |
| Perception and intention in relation to engineering: A gendered study based on a one-day outreach activity P Molina-Gaudo, S Baldassarri, M Villarroya-Gaudo, E Cerezo IEEE Transactions on Education 53 (1), 61-70, 2009 | 51 | 2009 |
| Store buffer design in first-level multibanked data caches EF Torres, P Ibánez, V Viñals, JM Llabería 32nd International Symposium on Computer Architecture (ISCA'05), 469-480, 2005 | 51 | 2005 |
Víctor Viñals-YúferaUniversidad de ZaragozaDirección de correo verificada de unizar.es
