Eduardo de la Torre
Título
Citado por
Citado por
Año
Design methodologies based on hardware description languages
T Riesgo, Y Torroja, E De la Torre
IEEE Transactions on Industrial electronics 46 (1), 3-12, 1999
1211999
A modular architecture for nodes in wireless sensor networks.
J Portilla, A De Castro, E De La Torre, T Riesgo
J. UCS 12 (3), 328-339, 2006
922006
Embedded runtime reconfigurable nodes for wireless sensor networks applications
YE Krasteva, J Portilla, E de la Torre, T Riesgo
IEEE Sensors Journal 11 (9), 1800-1810, 2011
752011
Using SRAM based FPGAs for power-aware high performance wireless sensor networks
J Valverde, A Otero, M Lopez, J Portilla, E De la Torre, T Riesgo
Sensors 12 (3), 2667-2692, 2012
582012
Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems
YE Krasteva, E De La Torre, T Riesgo, D Joly
2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006
572006
Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors
J Portilla, A Otero, E de la Torre, T Riesgo, O Stecklina, S Peter, ...
International Journal of Distributed Sensor Networks 6 (1), 740823, 2010
562010
Self-reconfigurable Evolvable Hardware System for Adaptive Image Processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
Transactions on Computers, 1-1, 2013
552013
A fast emulation-based NoC prototyping framework
YE Krasteva, F Criado, E de la Torre, T Riesgo
2008 International Conference on Reconfigurable Computing and FPGAs, 211-216, 2008
512008
Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs
YE Krasteva, AB Jimeno, E de la Torre, T Riesgo
16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 77-83, 2005
462005
Remote HW-SW reconfigurable wireless sensor nodes
YE Krasteva, J Portilla, JM Carnicer, E de la Torre, T Riesgo
Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE …, 2008
422008
Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems
R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo
2011 International Conference on Reconfigurable Computing and FPGAs, 164-169, 2011
392011
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems
A Otero, E de la Torre, T Riesgo
2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012
382012
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework
A Rodríguez, J Valverde, J Portilla, A , Otero, T Riesgo, E de la Torre
Sensors 18 (6), 1-30, 2018
342018
FPGAs: fundamentals, advanced features, and applications in industrial electronics
JJR Andina, E De la Torre Arnanz, MD Valdes
CRC Press, 2017
332017
Automatic generation of identical routing pairs for FPGA implemented DPL logic
W He, A Otero, E de la Torre, T Riesgo
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
302012
A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations
W He, E de la Torre, T Riesgo
2011 International Conference on Reconfigurable Computing and FPGAs, 217-222, 2011
292011
A Modular Peripheral to Support Self-Reconfiguration in SoCs
A Otero, Á Morales-Cas, J Portilla, E de la Torre, T Riesgo
Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th …, 2010
252010
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems
A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 336-343, 2011
242011
Power management techniques in an FPGA-based WSN node for high performance applications
M Lombardo, J Camarero, J Valverde, J Portilla, E de la Torre, T Riesgo
7th International Workshop on Reconfigurable and Communication-Centric …, 2012
222012
An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation
W He, E de la Torre, T Riesgo
International Workshop on Constructive Side-Channel Analysis and Secure …, 2012
222012
El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.
Artículos 1–20