Johnny Öberg
TitleCited byYear
A network on chip architecture and design methodology
S Kumar, A Jantsch, JP Soininen, M Forsell, M Millberg, J Oberg, ...
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms …, 2002
15892002
Networks on chip
A Jantsch, J Soininen, M Forsell, L Zheng, S Kumar, M Millberg, J Öberg
Workshop at the European Solid State Circuits Conference, 2001
9612001
Network on chip: An architecture for billion transistor era
A Hemani, A Jantsch, S Kumar, A Postula, J Oberg, M Millberg, ...
Proceeding of the IEEE NorChip Conference 31, 11, 2000
5762000
Load distribution with the proximity congestion awareness in a network on chip
E Nilsson, M Millberg, J Oberg, A Jantsch
2003 Design, Automation and Test in Europe Conference and Exhibition, 1126-1127, 2003
2102003
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
A Hemani, T Meincke, S Kumar, A Postula, T Olsson, P Nilsson, J Oberg, ...
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 873-878, 1999
2081999
Hardware/software partitioning and minimizing memory interface traffic
A Jantsch, P Ellervee, A Hemani, J Öberg, H Tenhunen
European Design Automation Conference: Proceedings of the conference on …, 1994
1361994
A case study on hardware/software partitioning
A Jantsch, P Ellervee, J Oberg, A Hemani
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 111-118, 1994
961994
Grammar-based hardware synthesis of data communication protocols
J OEberg, A Kumar, A Hemani
Proceedings of the 9th international symposium on System synthesis, 14, 1996
671996
Toward a scalable test methodology for 2D-mesh network-on-chips
K Petersén, J Oberg
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
612007
Globally asynchronous locally synchronous architecture for large high-performance ASICs
T Meincke, A Hemani, S Kumar, P Ellervee, J Oberg, T Olsson, P Nilsson, ...
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits …, 1999
561999
Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking
E Nilsson, J Öberg
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004
532004
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen
VLSI-SOC, 362-, 2003
292003
A NoC system generator for the Sea-of-Cores era
J Öberg, F Robino
Proceedings of the 8th FPGAWorld Conference, 1-6, 2011
282011
A NoC System generator for the Sea-of-Cores era
J Öberg, F Robino
FPGAWorld-2011, Proceedings of the 8th FPGAWorld Conference, Stockholm, 2011 …, 2011
282011
System level virtual prototyping of DSP SOCs using grammar based approach
A Hemani, AK Deb, J Oberg, A Postula, D Lindqvist, B Fjellborg
Design Automation for Embedded Systems 5 (3-4), 295-311, 2000
272000
Grammar based modelling and synthesis of device drivers and bus interfaces
M O'Nils, J Oberg, A Jantsch
Proceedings. 24th EUROMICRO Conference (Cat. No. 98EX204) 1, 55-58, 1998
271998
Grammar-based hardware synthesis from port-size independent specifications
J Oberg, A Kumar, A Hemani
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (2), 184-194, 2000
252000
ProGram: A Grammar-Based Method for Specification and Hardware Synthesis of Communication Protocols
J Öberg
221999
A software oriented approach to hardware/software codesign
A Jantsch, P Ellervee, J Oberg, A Hemani, H Tenhunen
Proc. of the Poster Session of CC, 1994
221994
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen
Integration 38 (1), 3-17, 2004
212004
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Articles 1–20