| Pipelined Radix- Feedforward FFT Architectures M Garrido, J Grajal, MA Sanchez, O Gustafsson IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (1), 23-32, 2011 | 275 | 2011 |
| A pipelined FFT architecture for real-valued signals M Garrido, KK Parhi, J Grajal IEEE Transactions on Circuits and Systems I: Regular Papers 56 (12), 2634-2643, 2009 | 163 | 2009 |
| Implementing FFT-based digital channelized receivers on FPGA platforms MA Sanchez, M Garrido, M Lopez-Vallejo, J Grajal IEEE Transactions on Aerospace and Electronic Systems 44 (4), 1567-1585, 2008 | 106 | 2008 |
| CORDIC II: a new improved CORDIC algorithm M Garrido, P Källström, M Kumm, O Gustafsson IEEE Transactions on Circuits and Systems II: Express Briefs 63 (2), 186-190, 2015 | 97 | 2015 |
| Optimum circuits for bit reversal M Garrido, J Grajal, O Gustafsson IEEE Transactions on Circuits and Systems II: Express Briefs 58 (10), 657-661, 2011 | 63 | 2011 |
| Efficient memoryless CORDIC for FFT computation M Garrido, J Grajal 2007 IEEE International Conference on Acoustics, Speech and Signal …, 2007 | 58 | 2007 |
| The serial commutator FFT M Garrido, SJ Huang, SG Chen, O Gustafsson IEEE Transactions on Circuits and Systems II: Express Briefs 63 (10), 974-978, 2016 | 52 | 2016 |
| The feedforward short-time Fourier transform M Garrido IEEE Transactions on Circuits and Systems II: Express Briefs 63 (9), 868-872, 2016 | 48 | 2016 |
| A survey on pipelined FFT hardware architectures M Garrido Journal of Signal Processing Systems 94 (11), 1345-1364, 2022 | 46 | 2022 |
| A 4096-point radix-4 memory-based FFT using DSP slices M Garrido, MÁ Sánchez, ML López-Vallejo, J Grajal IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 375-379, 2016 | 46 | 2016 |
| Continuous-flow parallel bit-reversal circuit for MDF and MDC FFT architectures SG Chen, SJ Huang, M Garrido, SJ Jou IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2869-2877, 2014 | 46 | 2014 |
| A new representation of FFT algorithms using triangular matrices M Garrido IEEE Transactions on Circuits and Systems I: Regular Papers 63 (10), 1737-1745, 2016 | 45 | 2016 |
| Challenging the limits of FFT performance on FPGAs M Garrido, M Acevedo, A Ehliar, O Gustafsson 2014 International Symposium on Integrated Circuits (ISIC), 172-175, 2014 | 43 | 2014 |
| Low-complexity multiplierless constant rotators based on combined coefficient selection and shift-and-add implementation (CCSSI) M Garrido, F Qureshi, O Gustafsson IEEE Transactions on Circuits and Systems I: Regular Papers 61 (7), 2002-2012, 2014 | 42 | 2014 |
| Digital channelised receivers on FPGAs platforms MA Sanchez, M Garrido, M López-Vallejo, J Grajal, C López-Barrio IEEE International Radar Conference, 2005., 816-821, 2005 | 41 | 2005 |
| Feedforward FFT hardware architectures based on rotator allocation M Garrido, SJ Huang, SG Chen IEEE Transactions on Circuits and Systems I: Regular Papers 65 (2), 581-592, 2017 | 38 | 2017 |
| A 512-point 8-parallel pipelined feedforward FFT for WPAN T Ahmed, M Garrido, O Gustafsson 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals …, 2011 | 38 | 2011 |
| Efficient hardware architectures for the computation of the FFT and other related signal processing algorithms in real time M Garrido Department of Signals and Systems, Radio communications, University of …, 2009 | 38 | 2009 |
| Multiplierless unity-gain SDF FFTs M Garrido, R Andersson, F Qureshi, O Gustafsson IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (9 …, 2016 | 36 | 2016 |
| Unified architecture for 2, 3, 4, 5, and 7‐point DFTs based on Winograd Fourier transform algorithm F Qureshi, M Garrido, O Gustafsson Electronics Letters 49 (5), 348-349, 2013 | 36 | 2013 |
Oscar GustafssonLinköping UniversityVerified email at liu.se
