Axel Jantsch
Axel Jantsch
TU Wien, Vienna, Austria (Vienna University of Technology)
Verified email at - Homepage
Cited by
Cited by
A network on chip architecture and design methodology
S Kumar, A Jantsch, JP Soininen, M Forsell, M Millberg, J Oberg, ...
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms†…, 2002
Networks on chip
A Jantsch, H Tenhunen
Kluwer Academic Publishers, 2003
Network on chip: An architecture for billion transistor era
A Hemani, A Jantsch, S Kumar, A Postula, J Oberg, M Millberg, ...
Proceeding of the IEEE NorChip Conference, 166-173, 2000
Network on chip: An architecture for billion transistor era
SKAPJ Oberg, MMA Hemani, A Jantsch, D Lindqvist
Proc. 18th IEEE Norchip Coference, 2000
Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
M Millberg, E Nilsson, R Thid, A Jantsch
Design, Automation and Test in Europe Conference and Exhibition, 2004†…, 2004
Modeling embedded systems and SoCs: concurrency and time in models of computation
A Jantsch
Morgan Kaufmann Pub, 2004
The Nostrum backbone-a communication protocol stack for networks on chip
M Millberg, E Nilsson, R Thid, S Kumar, A Jantsch
17th International Conference on VLSI Design. Proceedings., 693-696, 2004
System modeling and transformational design refinement in ForSyDe [formal system design]
I Sander, A Jantsch
IEEE Transactions on Computer-Aided Design of Integrated Circuits and†…, 2004
Load distribution with the proximity congestion awareness in a network on chip
E Nilsson, M Millberg, J Oberg, A Jantsch
2003 Design, Automation and Test in Europe Conference and Exhibition, 1126-1127, 2003
Methods for fault tolerance in networks-on-chip
M Radetzki, C Feng, X Zhao, A Jantsch
ACM Computing Surveys (CSUR) 46 (1), 1-38, 2013
Run-time partial reconfiguration speed investigation and architectural design space exploration
M Liu, W Kuehn, Z Lu, A Jantsch
2009 International Conference on Field Programmable Logic and Applications†…, 2009
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
H Zimmer, A Jantsch
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware†…, 2003
Hardware/software partitioning and minimizing memory interface traffic
A Jantsch, P Ellervee, A Hemani, J ÷berg, H Tenhunen
European Design Automation Conference: Proceedings of the conference on†…, 1994
Interconnect-centric design for advanced SoC and NoC
J Nurmi, J Isoaho, A Jantsch, H Tenhunen
Springer Science+ Business Media, Incorporated, 2005
Models of computation and languages for embedded system design
A Jantsch, I Sander
IEE Proceedings-Computers and Digital Techniques 152 (2), 114-129, 2005
Cluster-based simulated annealing for mapping cores onto 2D mesh networks on chip
Z Lu, L Xia, A Jantsch
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008†…, 2008
Simulation and Evaluation for a network on chip architecture using NS-2
YR Sun, S Kumar, A Jantsch
20th IEEE Norchip Conference, 2002
An analytical latency model for networks-on-chip
AE Kiasari, Z Lu, A Jantsch
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (1), 113-123, 2012
A case study on hardware/software partitioning
A Jantsch, P Ellervee, J Oberg, A Hemani
Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 111-118, 1994
Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router
C Feng, Z Lu, A Jantsch, M Zhang, Z Xing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (6†…, 2012
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