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Geert Janssen
Geert Janssen
IBM T.J. Watson Research Center
Verified email at us.ibm.com - Homepage
Title
Cited by
Cited by
Year
A performance study of BDD-based model checking
B Yang, RE Bryant, DR O’Hallaron, A Biere, O Coudert, G Janssen, ...
Formal Methods in Computer-Aided Design: Second International Conference …, 1998
1221998
Scalable sequential equivalence checking across arbitrary design transformations
J Baumgartner, H Mony, V Paruthi, R Kanzelman, G Janssen
2006 International Conference on Computer Design, 259-266, 2006
902006
Exploring power management in multi-core systems
R Bergamaschi, G Han, A Buyuktosunoglu, H Patel, I Nair, G Dittmann, ...
2008 Asia and South Pacific Design Automation Conference, 708-713, 2008
702008
Framework for multiple-engine based verification tools for integrated circuits
JR Baumgartner, G Janssen, A Kuehlmann, V Paruthi, LH Trevillyan
US Patent 6,698,003, 2004
59*2004
Asset health management using predictive and prescriptive analytics for the electric power grid
A Goyal, E Aprilia, G Janssen, Y Kim, T Kumar, R Mueller, D Phan, ...
IBM Journal of Research and Development 60 (1), 4: 1-4: 14, 2016
462016
Multicore power management: Ensuring robustness via early-stage formal verification
A Lungu, P Bose, DJ Sorin, S German, G Janssen
2009 7th IEEE/ACM International Conference on Formal Methods and Models for …, 2009
462009
Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis
MK Ganai, G Janssen, FK Krohm, A Kuehlmann, V Paruthi
US Patent 6,473,884, 2002
442002
The TiO2/electrolyte solution interface: I. Influence of pretreatment conditions and of impurities
MJG Janssen, HN Stein
Journal of colloid and interface science 109 (2), 508-515, 1986
411986
Exploiting structural similarities in a BDD-based verification method
CAJ Van Eijk, G Janssen
International Conference on Theorem Provers in Circuit Design, 110-125, 1994
391994
Method for preserving constraints during sequential reparameterization
JR Baumgartner, G Janssen, H Mony, V Paruthi
US Patent 7,299,432, 2007
382007
Logics for digital circuit verification: theory, algorithms, and applications
GLJM Janssen
371999
A consumer report on BDD packages
G Janssen
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
342003
The TiO2/electrolyte solution interface: II. Calculations by means of the site binding model
MJG Janssen, HN Stein
Journal of colloid and interface science 111 (1), 112-118, 1986
331986
Performance modeling for early analysis of multi-core systems
R Bergamaschi, I Nair, G Dittmann, H Patel, G Janssen, N Dhanwada, ...
Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007
292007
ROBDD software
G Janssen
Department of Electrical Engineering, Eindhoven University of Technology, 1993
241993
Tutorial on verification of distributed cache memory protocols
S German, G Janssen
Formal methods in computer aided design, 2004
202004
Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit
V Paruthi, C Jacobi, G Janssen, J Xu, KO Weber
US Patent 7,340,473, 2008
192008
Hardware verification using temporal logic: a practical view
G Janssen
Proc. IMEC-IFIP WG 10 (10.5), 291-300, 1989
191989
IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory
M Ohmacht, A Wang, T Gooding, B Nathanson, I Nair, G Janssen, ...
IBM Journal of Research and Development 57 (1/2), 7: 1-7: 12, 2013
182013
LWB–The Logics Workbench 1.1
G Jaeger, P Balsiger, A Heuerding, S Schwendimann, M Bianchi, ...
172000
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