Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI R Taco, I Levi, M Lanuzza, A Fish
Solid-State Electronics 117, 185-192, 2016
49 2016 An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 R Taco, I Levi, M Lanuzza, A Fish
IEEE Journal of Solid-State Circuits 54 (2), 560-568, 2018
35 2018 Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design R Taco, I Levi, A Fish, M Lanuzza
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
24 2014 A 0.8-V, 1.54-pJ/940-MHz dual-mode logic-based 16× 16-b booth multiplier in 16-nm FinFET N Shavit, I Stanger, R Taco, M Lanuzza, A Fish
IEEE Solid-State Circuits Letters 3, 314-317, 2020
19 2020 Ultralow voltage finFET-versus TFET-based STT-MRAM cells for IoT applications E Garzón, M Lanuzza, R Taco, S Strangio
Electronics 10 (15), 1756, 2021
18 2021 Reconfigurable CMOS/STT-MTJ non-volatile circuit for logic-in-memory applications E Garzón, B Zambrano, T Moposita, R Taco, LM Prócel, L Trojman
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020
18 2020 Dynamic gate-level body biasing for subthreshold digital design M Lanuzza, R Taco, D Albano
2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014
16 2014 Evaluation of dual mode logic in 28nm FD-SOI technology R Taco, I Levi, M Lanuzza, A Fish
2017 IEEE international symposium on circuits and systems (ISCAS), 1-4, 2017
15 2017 XNOR-bitcount operation exploiting computing-in-memory with STT-MRAMs A Musello, E Garzón, M Lanuzza, LM Prócel, R Taco
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (3), 1259-1263, 2023
13 2023 Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology R Taco, I Levi, M Lanuzza, A Fish
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 41-44, 2016
12 2016 Silicon evaluation of multimode dual mode logic for PVT-aware datapaths I Stanger, N Shavit, R Taco, M Lanuzza, A Fish
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1639-1643, 2020
11 2020 Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines D Albano, M Lanuzza, R Taco, F Crupi
International Journal of Circuit Theory and Applications 43 (11), 1523-1540, 2015
11 2015 Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits R Taco, M Lanuzza, D Albano
VLSI Design 2015, 8-8, 2015
11 2015 Dual mode logic address decoder L Yavits, R Taco, N Shavit, I Stanger, A Fish
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
9 2020 Energy efficient self-adaptive Dual Mode Logic address decoder K Vicuña, C Mosquera, A Musello, S Benedictis, M Rendón, E Garzón, ...
Electronics 10 (9), 1052, 2021
7 2021 Efficiency of dual mode logic in nanoscale technology nodes N Shavit, R Taco, A Fish
2018 IEEE International Conference on the Science of Electrical Engineering …, 2018
6 2018 Robust dual mode pass logic (DMPL) for energy efficiency and high performance I Stanger, N Shavit, R Taco, L Yavits, M Lanuzza, A Fish
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
5 2020 Process variation-aware datapath employing dual mode logic N Shavit, I Stanger, R Taco, A Fish
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
5 2018 DMTJ-based non-volatile ternary content addressable memory for energy-efficient high-performance systems K Vicuña, LM Prócel, L Trojman, R Taco
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 1-4, 2022
4 2022 Performance benchmarking of TFET and FinFET digital circuits from a synthesis-based perspective M Rendón, C Cao, K Landázuri, E Garzón, LM Prócel, R Taco
Electronics 11 (4), 632, 2022
4 2022 
Marco LanuzzaUniversity of CalabriaDirección de correo verificada de deis.unical.it
